Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2000-02-23
2001-10-23
Metjahic, Safet (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
Reexamination Certificate
active
06307388
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to electromechanical apparatus for testing integrated circuit chips. More particularly, the present invention relates to chip testing apparatus in which a chip holding subassembly, a power converter subassembly, and a temperature regulating subassembly are squeezed together in multiple sets by respective pressing mechanisms which exert a substantially constant force despite several dimensional variations in the apparatus.
Typically, a single IC chip contains more than one-hundred-thousand transistors. Thus, a manufacturer of IC chips must test the chips to ensure that they operate properly before they are sold to a customer. This testing is usually accomplished as follows.
Initially, one group of chips that are to be tested are placed in respective sockets that are mounted on several printed circuit boards. Each printed circuit board has edge connectors on one edge of the board; and those connectors carry test signals, as well as DC electrical power, for the chips that are in the sockets.
After the chips are placed in the sockets, the printed circuit boards are inserted into fixed slots in an electromechanical apparatus where the chip testing occurs. As each printed circuit board is inserted into a slot, the edge connectors on the board plug into mating connectors that are provided in the slot.
Usually, several printed circuit boards are held in the slots, spaced-apart from each other, in a horizontal row. Alternatively, several printed circuit boards can be held in the slots, spaced-apart from each other, in a vertical column.
Multiple signal lines are provided in the chip testing apparatus which extend from the connectors in the slots to a test signal controller. This controller tests the chips by sending signals to the chips and receiving responses from them. Also, electrical power lines are provided in the chip testing apparatus which extend from the connectors in the slots to one or more power supplies.
Often it is desirable to perform a “burn-in” test on the chips wherein the chips are held at a high temperature while they are tested. In the prior art, that was done by enclosing the chip testing apparatus in an oven and providing fans in the enclosure which circulate hot air past the chips while they are tested.
However, one drawback with the above prior art chip testing apparatus is that the temperature at which the chips are tested cannot be regulated accurately. This inaccuracy is caused, in part, by variations in the temperature and velocity of the air which flows past each of the chips. Also, the inaccuracy is caused by variations in chip power dissipation which occurs while the chips are being tested, and this problem gets worse as the magnitude of the power variations increase.
One prior art mechanism which accurately regulates the temperature of IC chips in a product where the chips are permanently held, such as a computer, is described in U.S. Pat. No. 4,809,134, by Tustaniwskyj, et al, which is entitled “Low Stress Liquid Cooling Assembly”. That assembly includes a hollow jacket which carries a liquid coolant and the jacket contacts each IC chip. Thus the temperature of the chips is regulated accurately by conduction.
However, in the above '134 assembly, the jackets are held in place on the chips by a beam; and several bolts must be removed before the jackets can be lifted off the chips. To use such an assembly in a chip-testing environment would be impractical because there, the jackets need to be repeatedly taken off one set of chips and put on another set of chips.
Also, another drawback with the above prior art chip testing apparatus is that due to the row/column arrangement of the printed circuit boards, a large distance inherently exists between the chips that are tested and the power supplies for those chips. Due to those large distances, parasitic resistances, parasitic inductances and parasitic capacitances are inherently large; and thus, the more difficult it becomes to keep the chip voltages constant while chip power dissipation changes rapidly as the chips are tested.
Accordingly, a primary object of the invention is to provide an improved electromechanical apparatus for testing IC chips which avoids the above drawbacks.
BRIEF SUMMARY OF THE INVENTION
The present invention, as claimed, covers the structure of an electromechanical apparatus for testing integrated circuit chips wherein a chip holding subassembly, a power converter subassembly, and a temperature regulating subassembly are squeezed together in multiple sets by respective pressing mechanisms. A major benefit which is achieved with this electromechanical apparatus is that by pressing the temperature regulating subassembly against the chip holding subassembly, heat can be added/removed from the chips by conduction; and thus the temperature of the chips can be regulated accurately. Another major benefit which is achieved with this electromechanical apparatus is that by pressing the power converter subassembly against the chip holding subassembly, the distance between the chips that are tested and the power supplies for those chips is made small. Consequently, the chip voltages can easily be kept constant while the chip power dissipation changes rapidly as the chips are tested.
In one embodiment, the chip holding subassemblies and the power converter subassemblies and the temperature regulating subassemblies are held by a frame in a vertical stack. Above each chip holding subassembly lies its power converter subassembly, and below each chip holding subassembly lies its temperature regulating subassembly. To press the subassemblies together, the pressing mechanisms move the temperature regulating subassemblies upward where they initially contact their chip holding subassembly, and then, the pressing mechanisms move both the chip holding subassemblies and the temperature regulating subassemblies further upward to a “closed” position where they contact their power converter subassembly.
All of the chips are tested while the subassemblies are pressed together in the closed position. Thereafter, when the testing is complete, the pressing mechanisms move the temperature regulating subassemblies and the chip holding subassemblies downward to an “open” position. There, the chip holding subassemblies are simply slid out of the frame, loaded with a new set of chips to be tested, and slid back into the frame.
All of the pressing mechanisms operate concurrently in response to a single actuator. Consequently, physical contact between the temperature regulating subassemblies and the chip holding subassemblies and the power converter subassemblies is made quickly, and is broken quickly. This quick connect/quick disconnect feature is very useful in a chip testing environment.
REFERENCES:
patent: 5572144 (1996-11-01), Davidson et al.
patent: 5966022 (1999-10-01), Budnaitis et al.
Babcock James Wittman
Brafford James Mason
Friedrich Lawrence William
Tustaniwskyj Jerry Ihor
Fassbender Charles J.
LeRoux Etienne P
Metjahic Safet
Rode Lise A.
Starr Mark T.
LandOfFree
Electromechanical apparatus for testing IC chips using first... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Electromechanical apparatus for testing IC chips using first..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electromechanical apparatus for testing IC chips using first... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2558635