Electromagnetic interference suppression device

Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means

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361111, 361118, H02H 900

Patent

active

051364557

ABSTRACT:
A multi-stage electromagnetic interference suppression circuit is disclosed which utilizes a diverter network, an impedance network and a clamping network. The diverter network includes a series combination of a varistor and a three terminal gas arrester to suppress incoming transient energy in both normal and common propagation modes. The clamping network serves to suppress any transient energy overshoot which is not suppressed by the diverter stage. Radio frequency interference is filtered by X and Y capacitors forming LC filters with an inductance in the impedance network.

REFERENCES:
patent: 3771022 (1973-11-01), Isokawa
patent: 4455586 (1984-06-01), McCartney
patent: 4563720 (1986-01-01), Clark
patent: 4586104 (1986-04-01), Standler
patent: 4628394 (1986-12-01), Crosby
patent: 4630163 (1986-12-01), Cooper et al.
patent: 4677518 (1987-06-01), Hershfield
patent: 4683514 (1987-07-01), Cook
patent: 4758920 (1988-07-01), McCartney
patent: 4760485 (1988-07-01), Ari et al.
patent: 4901183 (1990-02-01), Lee
"IEEE Guide for Surge Voltages in Low Voltage AC Power Circuits", IEEE Power Engineering Society, IEEE Std. 587-1980, Approved Dec. 19, 1979.

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