Data processing: measuring – calibrating – or testing – Measurement system in a specific environment – Electrical signal parameter measurement system
Reexamination Certificate
2002-07-12
2004-06-22
Hoff, Marc S. (Department: 2857)
Data processing: measuring, calibrating, or testing
Measurement system in a specific environment
Electrical signal parameter measurement system
C702S066000, C702S070000, C702S116000, C702S190000, C324S750010, C703S019000, C438S026000, C438S063000, C361S099000, C361S816000, C361S818000
Reexamination Certificate
active
06754598
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an electromagnetic interference (EMI) analysis method and apparatus, and more particularly, to a method capable of carrying out an EMI analysis at a high speed with high precision for a large-scaled high-speed driving LSI (Large-Scaled Semiconductor Integrated Circuit). The method also allows for analyzing an electromagnetic interference in the case in which there is no current information.
The utilization range of the LSI has been enlarged to a communication apparatus such as a mobile telephone, general home products, toys and automobiles as well as a computer. On the other hand, there is a problem in that electromagnetic interference generated from these products causes radio interference noise for receivers contained in, for example, a television or a radio and/or the malfunction of other systems. Countermeasure for preventing such interference, such as, filtering or shielding has also been attempted to solve such problems. However, the noise suppression of an LSI package has been highly demanded as a result of an increase in the number of components, an increase in a cost and the difficulty to take effective countermeasure.
Under the circumstances, the LSI is positioned as a key device in each product, and an increase in the scale and speed of the LSI has been required to maintain the competition power of the product. In order to meet these requirements with a reduction in the product cycle, it is necessary to automate the LSI design. The necessity of employing a synchronous design has been increased as the present conditions for introducing a design automation technology.
As shown in
FIG. 30
, conventionally, there has been proposed a method in which an LPE (layout element extraction) processing for creating a netlist (a circuit connection information file) including a parasitic resistance and a capacitance component is executed by using an EMI dedicated library
3101
and layout information
3102
which are obtained by previously characterizing the internal capacitance and input capacitance of a cell (step
3103
) and the total capacitance of a block is calculated (step
3105
).
Similarly, a block netlist
3106
is also subjected to the LPE, and the supply current of the block is calculated under the condition of no resistance of the power supply line and no supply capacitance of the power supply line (step
3107
), and thereby, the current on the power supply line can be obtained.
Moreover, the current model of the total block capacitance and supply current is connected to a power netlist
3104
which is subjected to the LPE in the same manner.
The connection information is subjected to a transistor level simulation, thereby estimating an EMI noise (step
3109
).
Thus, an EMI spectrum
3110
is obtained.
However, when utilizing this method, there is a problem in that a special library for capacitance estimation is required.
Moreover, since a transistor level simulator is used for the supply current calculation, there is a problem in that a very long time is required for the operation.
Furthermore, since the LEP is carried out including a power supply, a very long time is required for the operation.
In addition, the power netlist, the capacitance information and the supply current information are collectively subjected to the transistor level simulation. For this reason, there is a problem in that a very long time is also required for this operation.
Therefore, in order to increase the speed of the operation, there has been proposed a method of extracting an RLC by means of an impedance analyzer.
In this method, as shown in
FIG. 31
, R
3203
, L
3204
and C
3205
are calculated from LSI information
3201
by using an impedance analyzer
3202
. Then, these values, a supply current spectrum
3210
obtained by carrying out a supply current estimation
3209
on a gate level from a load capacitance
3206
, a gate level netlist
3207
and a test vector
3208
, and the supply current spectrum
3210
and the RLC are used to carry out an EMI estimation (step
3211
) so that an EMI spectrum
3212
is obtained.
In this method, the supply current can be estimated on the gate level. Therefore, the operation can be carried out at a high speed.
Moreover, since the RLC information capable of being obtained from an actual chip at a high speed is used, the speed of the processing can be increased.
Furthermore, in the EMI estimation, the frequency response of a power measuring system netlist determined from the RLC information is multiplied by the supply current spectrum without using the transistor level simulation. Therefore, the speed of the operation can be increased.
In addition, an analysis is carried out based on information to be used in a standard gate level verification flow. Consequently, special processing and particular information are not required.
However, this method is based on the results of actual measurements. For this reason, there has conventionally been a problem in that a method of accurately predicting the RLC in the design stage cannot be proposed.
Although the speed is higher than that of the transistor level simulation, the gate level simulation is still required. Therefore, there has been a problem in that a long time is required for the operation.
Moreover, there has been a problem in that the prediction is difficult in a floor plan stage in which a netlist is not determined.
Under the circumstances described above, in the LSI design, it is apparent that the EMI should be estimated as early as possible and the design should be changed in the early stages when necessary in order to obtain the shortest technique for easily carrying out reliable LSI design. Utilizing the known techniques, however, there is no method of carrying out the EMI analysis in the floor plan stage prior to the LSI design.
SUMMARY OF THE INVENTION
The invention has been made in consideration of the foregoing problems and it is an object of the present invention to provide an electromagnetic interference analysis method and apparatus which can carry out an EMI analysis in the early stage of a design and which can reflect the information of a circuit and a package on a calculation while performing a high-speed analysis, thereby evaluating the electromagnetic interference of an LSI on a simulation in actual time.
In particular, the invention has an object to provide a method capable of carrying out an EMI analysis in a floor plan stage without calculating supply current information.
The invention provides a method of analyzing an electromagnetic interference amount of an LSI, including an equivalent impedance information calculating step of calculating and estimating equivalent impedance information based on circuit information of an LSI chip and package information of the LSI chip, and an electromagnetic interference noise calculating step of calculating an electromagnetic interference noise based on the equivalent impedance information.
According to such a structure, the equivalent impedance information is calculated from the circuit information and the package information without calculating the supply current information from the circuit information of the LSI chip, and a capacitance countermeasure correction is then carried out. Therefore, an electromagnetic interference analysis can easily be performed at a high speed. Moreover, the analysis can be carried out based on only the circuit information in the early design stage. Consequently, a chip area, a power supply or a package can easily be changed, the degree of freedom for taking an electromagnetic interference countermeasure can be increased and electromagnetic interference can be reduced.
Moreover, it is desirable that the equivalent impedance information calculating step should include a first extracting step of extracting a chip area, a power pad position and power supply information from the circuit information and a second extracting step of extracting a package type from the package information, and equivalent impedance information should be calculated and estimate
Hirano Shouzou
Shimazaki Kenji
Tsujikawa Hiroyuki
Desta Elias
Hoff Marc S.
Matsushita Electric - Industrial Co., Ltd.
McDermott & Will & Emery
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