Cutting – Processes
Reexamination Certificate
1995-05-12
2002-11-26
Dexter, Clark F. (Department: 3724)
Cutting
Processes
C083S526000, C083S575000, C083S588000, C083S929100, C335S277000, C400S167000
Reexamination Certificate
active
06484613
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to via and through hole structures especially for parallel processor packages having a plurality of printed circuit cards and/or boards, e.g., dedicated printed circuit cards and/or boards, for carrying processors, memory, and processor/memory elements. The printed circuit cards and/or boards are mounted on and interconnected through a plurality of circuitized flexible cable substrates, i.e., flex strips. The circuitized flexible cable substrates, i.e., flex strips, connect the separate printed circuit boards and cards through a central laminate portion. This central laminate portion provides Z-axis, layer to layer means for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication through vias and through holes extending from flex strip to flex strip through the laminate. The punch press method and apparatus of the invention provides electromagnetic braking of the punch press, thereby reducing bounceback and problems concomitant therewith.
BACKGROUND OF THE INVENTION
Parallel processors have a plurality of individual processors, all capable of cooperating on the same program. Parallel processors can be divided into Multiple Instruction Multiple Data (MIMD) and Single Instruction Multiple Data (SIMD) designs.
Multiple Instruction Multiple Data (MIMD) parallel processors have individual processing nodes characterized by fast microprocessors supported by many memory chips and a memory hierarchy. High performance inter node communications coprocessor chips provide the communications links to other microprocessors. Each processor node runs an operating system kernel, with communications at the application level being through a standardized library of message passing functions. In the MIMD parallel processor both shared and distributed memory models are supported.
Single Instruction Multiple Data (SIMD) parallel processors have a plurality of individual processor elements under the control of a single control unit and connected by an intercommunication unit. SIMD machines have an architecture that is specified by:
1. The number of processing elements in the machine.
2. The number of instructions that can be directly executed by the control unit. This includes both scalar instructions and program flow instructions.
3. The number of instructions broadcast by the control unit to all of the processor elements for parallel execution.
This includes arithmetic, logic, data routing, masking, and local operations executed by each active processor element over data within the processor element.
4. The number of masking schemes, where each mask partitions the set of processor elements into enabled and disabled subsets.
5. The number of data routing functions, which specify the patterns to be set up in the interconnection network for inter-processor element communications.
SIMD processors have a large number of specialized support chips to support dozens to hundreds of fixed point data flows. Instructions come from outside the individual node, and distributed memory is supported.
Parallel processors require a complex and sophisticated intercommunication network for processor-processor and processor-memory communications. The topology of the interconnection network can be either static or dynamic. Static networks are formed of point-to-point direct connections which will not change during program execution. Dynamic networks are implemented with switched channels which can dynamically reconfigure to match the communications requirements of the programs running on the parallel processor.
Dynamic networks are particularly preferred for multi-purpose and general purpose applications, Dynamic networks can implement communications patterns based on a program demands. Dynamic networking is provided by one or more of bus systems, multistage intercommunications networks, and crossbar switch networks.
Critical to all parallel processors, and especially to dynamic networks is the packaging of the interconnection circuitry. Specifically, the interconnection must provide high speed switching, with low signal attenuation, low crosstalk, and low noise.
SUMMARY OF THE INVENTION
The invention relates to methods and apparatus for fabricating parallel processor packages. The parallel processor packages have a plurality of printed circuit cards and/or boards, e.g., dedicated printed circuit cards and/or boards, for carrying processors, memory, and processor/memory elements. The printed circuit cards and/or boards are mounted on a plurality of circuitized flexible substrates, i.e., flex strips. The circuitized flexible substrates connect the separate printed circuit boards and cards through a relatively rigid central laminate portion. This central laminate portion provides means, e.g. Z-axis means, for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication.
Parallel processor systems have a plurality of individual processors, e.g., microprocessors, and a plurality of memory modules. The processors and the memory can be arrayed in one of several interconnection topologies, e.g., an SIMD (single instruction/multiple data) or an MIMD (multiple instruction/multiple data).
The memory modules and the microprocessors communicate through various topologies, as hypercubes, and toroidal networks, solely by way of exemplification and not limitation, among others. These inter-element communication topologies have various physical realizations. According to the invention described in the commonly assigned, copending U.S. Patent Applications listed above the individual logic and memory elements are on printed circuit boards and cards. These printed circuit boards and cards are, in turn, mounted on or otherwise connected to circuitized flexible substrates extending outwardly from a relatively rigid, circuitized laminate of the individual circuitized flexible substrates. The intercommunication is provided through a switch structure that is implemented in the laminate. This switch structure, which connects each microprocessor to each and every other microprocessor in the parallel processor, and to each memory module in the parallel processor, has the physical structure shown in FIG.
1
and the logical/electrical structure shown in FIG.
2
.
More particularly, the preferred physical embodiment of this electrical and logical structure is a multilayer switch structure shown in FIG.
1
. This switch structure provides separate layers of flex
21
for each unit or pairs of units, that is, each microprocessor, each memory module, or each microprocessor/memory element. The planar circuitization, as data lines, address lines, and control lines are on the individual printed circuit boards and cards
25
, which are connected through the circuitized flex
21
, and communicate with other layers of flex through Z-axis circuitization (vias and through holes) in the central laminate portion
41
in FIG.
1
. The bus structure is illustrated in
FIG. 2
, which shows a single bus, connecting a plurality of memory units through a bus, represented by OR-gates, to four processors. The Address Bus, Address Decoding Logic, and Read/Write Logic are not shown. The portion of the parallel processor represented by the OR gates, the inputs to the OR gates, and the outputs from the OR gates is carried by the laminated flex structure
41
.
Structurally the parallel processor
11
has a plurality of integrated circuit chips
29
, as processor chips
29
a
mounted on a plurality of printed circuit boards and cards
25
. For example, the parallel processor structure
11
of our invention includes a first processor integrated circuit printed circuit board
25
having a first processor integrated circuit chip
29
a
mounted thereon and a second processor integrated circuit printed circuit board
25
having a second processor integrated circuit chip
29
a
mounted thereon.
Analogous structures exist for the memory integrated circuit chips
29
b
, the parallel processor
11
h
Lee Ho Chong
Subbarayan Ganesh
Wilkin Paul Gerard
Dexter Clark F.
Schmeiser Olsen & Watts
LandOfFree
Electromagnetic bounce back braking for punch press and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Electromagnetic bounce back braking for punch press and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electromagnetic bounce back braking for punch press and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2931152