Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Depositing predominantly single metal coating
Reexamination Certificate
2001-03-14
2004-08-31
Nicolas, Wesley A. (Department: 1742)
Electrolysis: processes, compositions used therein, and methods
Electrolytic coating
Depositing predominantly single metal coating
C205S103000, C205S291000, C205S239000, C205S270000, C205S125000, C205S148000, C204SDIG009
Reexamination Certificate
active
06783654
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an electrolytic plating method and device filling up a microvia hole formed on a wiring board with metal plating.
2. Description of the Related Art
For electric appliances such as a cellular phone, a video camera, a notebook computer, etc., it is demanded to mount high-density components. As an implementation of high-density mounting, a buildup board on which a wiring layer and an insulation layer are sequentially formed, a printed-circuit board of an all-layer microvia type to which wiring boards on which microvias are formed are attached with heat and pressure, etc. are proposed.
For a conventional buildup board, micro holes (microvia holes) are formed on an insulation layer, and the inner side and the bottom of the holes are metal-plated, so that wiring layers above and below the insulation layer are electrically connected.
With this method, however, it is difficult to further form one microvia hole on another, and to securely connect the holes in an electric manner. Therefore, a land cannot be arranged on a microvia hole after microvia holes are stacked. Due to such a restriction on a pattern design, the whole of a pattern design cannot be made with an automatic wiring tool, and part of the design must be made manually. As a result, the time period required to design a printed-circuit board becomes long.
To overcome such a problem, a technique filling up microvia holes with electrolytic plating is proposed. For example, Japanese Laid-open Patent Publication Heisei 11, No. 8469 discloses the technique of filling up microvia holes by performing electric metal plating with PR electrolysis after an electroless metal film is formed.
However, with the plating method using PR electrolysis disclosed by the above described publication, plating must be performed for a long time (for example, two hours or longer) to fill up microvia holes. Therefore, the manufacturing cost of a printed-circuit board increases, and it is difficult to use a printed-circuit board on a mass-production level. Additionally, attempts are made to improve the density of an electric current in order to shorten a plating time. However, problems such that a void occurs during plating, or a plated surface becomes rough occur.
Furthermore, to solve the problems occurring when a soluble anode is used, for example, Japanese Laid-open Patent Publication Heisei 8, No. 507106 discloses a metal plating method using an insoluble anode and a plating solution to which an oxidation-reduction compound is added
The above described invention assumes electrolytic plating using a direct current power source, and does not present a plating method for filling up microvia holes on a printed-circuit board for a short time.
SUMMARY OF THE INVENTION
An object of the present invention aims at filling up microvia holes on a printed-circuit board for a short time.
According to the present invention, a printed-circuit board is used as one pole and an insoluble electrode is used as the other, and electrolytic plating is performed by applying a forward/reverse current with the use of a metal plating solution including iron ions by 0.1 gram/liter or more, so that microvia holes formed on a printed-circuit board are filled up with metal plating.
According to the present invention, electrolytic plating is performed by applying a forward/reverse current with the use of a metal plating solution including iron ions by 0.1 gram/liter or more, whereby microvia holes can be filled up for a time shorter than a conventional method, and a metal film having a smooth surface characteristic can be formed. As a result, microvias which electrically connect wiring layers above and below an insulation layer can be formed for a short time, thereby significantly reducing the manufacturing cost of a multi-layer printed-circuit board.
As an electrolytic plating method, for example, a pulse reverse electrolytic method applying a forward/reverse pulsed current is available.
Additionally, a plating solution may be stirred to flow in parallel with the surface to be plated of a printed-circuit board. At this time, the flow quantity of the plating solution may be controlled depending on the diameter or the depth of a microvia hole.
With the above described configuration, the deposit speed of metal plating on the surface of a printed-circuit board and that of metal plating within a microvia hole can be suitably controlled. Consequently, a deep microvia hole with a short diameter can be filled up without causing a void, etc. within the hole.
REFERENCES:
patent: 4292144 (1981-09-01), Lepetit et al.
patent: 5683564 (1997-11-01), Reynolds
patent: 5976341 (1999-11-01), Schumacher et al.
patent: 6099711 (2000-08-01), Dahms et al.
patent: 6129830 (2000-10-01), Senge et al.
patent: 6537439 (2003-03-01), Hauptmann et al.
patent: A-8-507106 (1996-07-01), None
patent: A-11-8469 (1999-01-01), None
Copy of the Official Letter of Aug. 4, 2003 with English Translation. German Patents DE 195 45 231 A1 and DE 43 44 387 C2 mentioned in Official Letter have English Equivalents 5,976,341 and 6,099,711 which were cited in U.S. 1stOfficial Action mailed Nov. 5, 2002.
Inoue Toshiki
Kumagai Kyoko
Kabushiki Kaisha Toyoda Jidoshokki Seisakusho
Nicolas Wesley A.
Woodcock & Washburn LLP
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