Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Coating selected area
Reexamination Certificate
1999-05-17
2002-09-03
Nguyen, Nam (Department: 1741)
Electrolysis: processes, compositions used therein, and methods
Electrolytic coating
Coating selected area
C205S125000, C205S291000, C205S296000
Reexamination Certificate
active
06444110
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to copper electroplating solutions, methods for using the solutions and products formed by using such methods and solutions. More particularly, the invention provides electrolytic copper plating solutions that have increased brightener levels and use of same for effective plating of high aspect ratio apertures, e.g. microvias with aspect ratios of at least 4:1 and diameters of 200 nm or smaller.
2. Background
Electroplating articles with copper coatings is generally well known in the industry. Electroplating methods involve passing a current between two electrodes in a plating solution where one electrode is the article to be plated. A common plating solution would be an acid copper plating solution containing (1) a dissolved copper salt (such as copper sulfate), (2) an acidic electrolyte (such as sulfuric acid) in an amount sufficient to impart conductivity to the bath and (3) additives (such as surfactants, brighteners, levelers and suppressants) to enhance the effectiveness and quality of plating. See generally U.S. Pat. Nos. 5,068,013; 5,174,886; 5,051,154; 3,876,513; and 5,068,013 for a discussion of copper plating baths.
Over time, a number of improvements in electroplating techniques have been made as the articles to be plated evolved in degree of difficulty and standards for plating increased. However, even with the improvements in electroplating techniques, circumstances exist that can lead to plating defects.
Copper plating technology has been particularly important in the manufacture of computer circuit boards. More specifically, during circuit board manufacture, copper electrical connections are provided between various board layers by plating board through holes whereby a thin conductive copper conductive is first applied, typically using electroless copper plating techniques, followed by electroplating copper from acid copper solutions.
Copper plating is also employed in circuit board manufacture to plate outer layers where final circuitry is defined. For such applications, panel plating is typically employed, where the full circuit board surface is copper plated followed by photodefining circuitry with a photoresist and then etching in a subtractive process. Alternatively an additive process can be employed, where copper circuits are produced by plating between lines defined by a resist relief image.
More recently, copper plating also has been employed in semiconductor chip manufacture to provide chip interconnections. Traditionally, semiconductors have been interconnected through aluminum conductors. However, industry continually demands enhanced performance, including ultra large-scale integration and faster circuits. Consequently, chip interconnects are required at dimensions of 200 nm and less. At such geometries, the resistivity of aluminum (theoretically 2.65×10
−8
ohm/meter at room temperature) is considered too high to allow the electronic signal to pass at required speeds. Copper, with a theoretical resistivity of 1.678×10
−8
ohm/meter, is considered a more suitable material to meet the next generation of semiconductor microchips.
Typical processes for defining semiconductor chip interconnects, particularly aluminum interconnects, have involved reactive ion etching of metal layers, e.g. a process that includes metal deposition, photolithographic patterning, line definition through reactive ion etching and dielectric deposition. However, in Cu-based systems, reactive ion etching is not practical as a result of the paucity of copper compounds with vapor pressures sufficient to enable removal of the copper as may be desired.
Consequently, alternative strategies have developed, such as the Damascene process. That process starts with deposition of dielectric typically by chemical vapor deposition of silicon materials or organic dielectrics followed by curing, or spin coating silicon materials or organic dielectrics. Patterning by photolithographic processes and reactive ion etching defines the vias and trenches (interconnects) in the dielectric. Barrier layers are then formed by chemical vapor deposition or other methods to isolate the copper lines from the dielectric. Copper is then deposited and excess material removed by chemical or mechanical polishing processes.
Although conventional copper plating systems can be suitable for plating vias and trenches as small as 300 nm with 4:1 aspect ratios, defects such as seams, voids and inclusions can occur with conventional methods when attempting to plate features that are smaller or have higher aspect ratios. Such defects can occur as a result of conformal copper plating, i.e. where all targeted surfaces are plated at the same rate such that the sidewalls of a via or trench plate together forming a seam or a demarcation of disruption where the copper grains are separated and will not anneal to form a continuous copper wire. Defects also will occur at the top rim of a via hole, where electronic charge density can concentrate and result in rapid copper growth that closes off the via before the via is filled sufficiently with metal. Such inadequate metal fill can result in inclusion and voids, disrupting the ability of the plated metal to carry a coherent signal.
It thus would be desirable to have new electroplating compositions. It would be particularly desirable to have new copper electroplating compositions that can plate effectively (e.g. absence of voids, inclusions and seams) high aspect ratio apertures, including high aspect ratio microvias as discussed above.
SUMMARY OF THE INVENTION
We have now found copper electroplating compositions that effectively plate a wide variety of articles, including printed circuit boards and other electronic packaging devices. Compositions and methods of the invention are particularly useful for filling microvias and trenches required by current and anticipated semiconductor fabrication requirements (including microvias having aspect ratios of at least 4:1 and diameters of 200 nm or less) by reliably plating copper deposits that are essentially or completely free of voids, inclusions or other plating imperfections.
Electroplating baths of the invention are characterized in significant part by comprising enhanced brightener concentrations. Without being bound by any theory, it is believed that the higher brightener concentrations can accelerate the plating rate in recesses and microvias as carrier molecules become incorporated into the plating deposit. This is counterintuitive to conventional thought and a completely unexpected result.
In particular, preferred electroplating compositions of the invention have a brightener concentration of at least about 1.5 mg per liter of plating solution (1.5 mg/L), more preferably a brightener concentration of at least about 1.75 mg per liter, still more preferably at least about 2.0, 2.5. 3, 3.5 or 4 mg of brightener per liter of plating solution. Good results have been achieved with even higher brightener concentrations, e.g. copper plating baths having a brightener concentration of at least about 5 mg per liter, or at least about 6, 7, 8, 9, 10, 12, 14, 16, 18, 20 or 25 mg/L, or even higher brightener concentrations such as at least about 30, 35, 40, 45, 50, 55 or 60 mg of brightener per liter of plating solution.
Preferably, the brightener concentration is maintained at such high concentrations throughout the entire or at least substantial portion of a plating cycle. Such maintenance of brightener concentrations entails regular addition of brightener during a plating cycle as the brightener component plates out. Brightener concentrations and replenishment rates during a plating cycle can be readily determined by known methods, such as the CPVS method as disclosed in U.S. Pat. Nos. 5,252,196 and 5,223,118, both assigned to the Shipley Company, or by the cyclic voltammetric stripping (CVS) methods.
In addition to such an elevated brightener concentration, preferably the plating bath also contains a surfactant-type suppressor agen
Barstad Leon R.
Lefebvre Mark
Martin James L.
Menard Stephane
Rychwalski James E.
Corless Peter F.
Frickey Darryl P.
Nguyen Nam
Nicolas Wesley A.
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