Electroless CU deposition on a barrier layer by CU contact displ

Details Electroless CU deposition on a barrier layer by CU contact displ Electroless CU deposition on a barrier layer by CU contact displ

1996-01-16

1999-04-06

Lusignan, Michael

Coating processes

Electrical product produced

Integrated circuit, printed circuit, or circuit board

427305, 427355, 427427, 4274431, 438631, 438633, 438678, B05D 512

Patent

active

058915133

ABSTRACT:
A method of utilizing electroless copper deposition to form interconnects on a semiconductor wafer. Once a via or a trench is formed in a dielectric layer, a titanium nitride (TiN) or tantalum (Ta) barrier layer is blanket deposited. Then, a contact displacement technique is used to form a thin activation seed layer of copper on the barrier layer. An electroless deposition technique is then used to auto-catalytically deposit copper on the activated barrier layer. The electroless copper deposition continues until the via/trench is filled. Subsequently, the surface is polished by an application of chemical-mechanical polishing (CMP) to remove excess copper and barrier material from the surface, so that the only copper and barrier material remaining are in the via/trench openings. Then an overlying silicon nitride (SiN) layer is formed above the exposed copper in order to form a dielectric barrier layer. The copper interconnect is fully encapsulated from the adjacent material by the TiN (or Ta) and the SiN layers.

REFERENCES:
patent: 4574095 (1986-03-01), Baum et al.
patent: 4789648 (1988-12-01), Chow et al.
patent: 4894260 (1990-01-01), Kumasaka et al.
patent: 4985750 (1991-01-01), Hoshino
patent: 5151168 (1992-09-01), Gilton et al.
patent: 5240497 (1993-08-01), Shacham et al.
patent: 5358907 (1994-10-01), Wong
patent: 5674787 (1997-10-01), Zhao et al.
B. Luther et al., 1993 VMIC Conference, Jun. 8-9, 1993, pp. 15-21.
Palmans et al., Conf. Proc. ULSI-X, Materials Research Society, pp. 87-94, (no month) 1995.
Cho et al. MRS Bulletin, pp. 31-38, Jun. 1993.
Mak, MRS Bulletin, pp. 55-62, Aug, 1994.
"Copper Interconnection with Tungsten Cladding for ULSI"; J.S.H. Cho et al.; VLSI Tech. Symp.; 1991; pp. 39-40. (no month).
"Encapsulated Copper Interconnection Devices Using Sidewall Barriers;" Donald S. Gardner et al.; 1991 VMIC Conference; Jun. 11-12, 1991; pp. 99-108.
"Planar Copper-Polyimide Back End Of The Line Interconnections For ULSI Devices;" B. Luther et al.; 1993 VMIC Conference; Jun. 8-9, 1993; pp. 15-21.
"Electroless Cu for VLSI;" James S.H. Cho et al.; MRS Bulletin/Jun. 1993; pp. 31-38.
"Electroless Copper Deposition on Metals and Metal Silicides;" Cecilia Y. Mak; MRS Bulletin/Aug. 1994; pp. 55-62.
"Development Of An Electroless Copper Deposition Bath For Via Fill Applications On TiN Seed Layers;" Roger Palmans et al.; Conf. Proc. ULSI-X; Materials Research Society; 1995; pp.87-94. (no month).
"Selective and Blanket Electroless Cu Plating Initiated By Contact Displacement For Deep Submicron Via Contact Filling;" Dubin et al.; VMIC Conf.; Jun. 27-29, 1995; pp. 315-321.
"0.35 um Cu-Filled Via Holes By Blanket Deposited Electroless Copper On Sputtered Seed Layer;" Yosi Shacham-Diamand et al.; VMIC Conf.; Jun. 27-29, 1995; pp.334-336.
"Barriers Against Copper Diffusion into Silicon and Drift Through Silicon Dioxide;" Shi-Qing Wang; MRS Bulletin/Aug. 1994; pp. 30-40.
"Inlaid Copper Multilevel Interconnections Using Planarization by Chemical-Mechanical Polishing;" S.P. Murarka et al.; MRS Bulletin/Jun. 1993; pp. 46-51.
"Electrochemically Deposited Diffusion Barriers;" M. Paunovic; et al.; J. Electrochem. Soc., vol. 141 No. 7; Jul. 1994; pp. 1843-1850.
"Electroless Copper Deposition For Multilevel Metallization;" S. Simon Wong et al.; Mat. Res. Soc. Symp. Proc. vol. 203; 1991 Materials Research Society; pp. 347-356. (no month).
"Electroless plating of copper at a low pH level;" R. Jagannathan et al.;IBM J. Res. Develop. vol. 37 No.2; Mar. 1993; pp. 117-123.
"Selective Electroless Metal Deposition for Integrated Circuit Fabrication;" Chiu H. Ting et al.; J. Electrochem. Soc. vol. 136, No.2; Feb. 1989; pp.456-462.
"Selective Electroless Metal Deposition for Via Hole Filling in VLSI Multilevel Interconnection Structures;" Chiu H. Ting et al.; J. Electrochem. Soc., vol. 136, No. 2; Feb. 1989; pp. 462-466.
"Pd/Si plasma immersion ion implantation for selective electroless copper plating on SiO2;" M.-H. Kiang et al.; Appl. Phys. Lett. 60 (22); Jun. 1, 1992; pp. 2767-2769.
"Selective electroless Ni deposition on a TiW underlayer for integrated circuit fabrication;" V.M. Dubin et al.; Thin Solid Films, 226(1993) ; pp. 87-93.
"Copper Corrosion With and Without Inhibitors;" V. Brusic et al.; J. Electrochem. Soc., vol. 138, No. 8; Aug. 1991; pp. 2253-2259.
"nm wide copper lines made by selective electroless deposition;" Yosi Shacham-Diamand; J. Micromech. Microeng. 1 (1991); pp. 66-72. (no month).
"Passivation of Copper by Silicide Formation In Dilute Silane;" S. Hymes et al.; Conf. Proc. ULSI-VII, Materials Research Society; 1992; pp. 425-431. (no month).
"A Half-Micron Pitch Cu Interconnection Technology;" Kazuyoshi Ueno et al.; 1995 Symposium on VLSI Technology Digest of Technical Papers; 1995; pp. 27-28. (no month).

Affiliated with

Also associated with

Rating

Electroless CU deposition on a barrier layer by CU contact displ does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Electroless CU deposition on a barrier layer by CU contact displ, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electroless CU deposition on a barrier layer by CU contact displ will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1369141