Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
2007-10-11
2008-11-25
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C257SE21022, C205S119000, C205S123000, C205S183000, C438S381000, C438S677000, C438S372000, C438S692000, C438S466000
Reexamination Certificate
active
07456030
ABSTRACT:
A hybrid method of fabricating magnetic core elements of an on-chip inductor structure addresses issues associated with conventional bottom up and damascene magnetic core plating techniques. The process uses two seed layers: a low resistance seed layer that solves the IR drop problem associated with the damascene plating techniques and a high resistance seed layer that is local to magnetic core features thus avoiding eddy current related performance degradation associated with the bottom up techniques.
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Fourson George
National Semiconductor Corporation
Stallman & Pollock LLP
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