Electroformed metallization

Semiconductor device manufacturing: process – Making device or circuit emissive of nonelectrical signal – Including integrally formed optical element

Reexamination Certificate

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Details

C438S652000, C438S678000, C257SE21159, C257SE21174, C257SE21295, C257SE21477, C257SE21479

Reexamination Certificate

active

10871938

ABSTRACT:
A method is provided for electroforming metal integrated circuit structures. The method comprises: forming an opening such as a via or line through an interlevel insulator, exposing a substrate surface; forming a base layer overlying the interlevel insulator and substrate surface; forming a strike layer overlying the base layer; forming a top layer overlying the strike layer; selectively etching to remove the top layer overlying the substrate surface, exposing a strike layer surface; and, electroforming a metal structure overlying the strike layer surface. The electroformed metal structure is deposited using an electroplating or electroless deposition process. Typically, the metal is Cu, Au, Ir, Ru, Rh, Pd, Os, Pt, or Ag. The base, strike, and top layers can be deposited using physical vapor deposition (PVD), evaporation, reactive sputtering, or metal organic chemical vapor deposition (MOCVD).

REFERENCES:
patent: 6613663 (2003-09-01), Furuya
patent: 6624060 (2003-09-01), Chen et al.
patent: 6740577 (2004-05-01), Jin et al.
patent: 6753254 (2004-06-01), Sandhu et al.
patent: 2003/0060041 (2003-03-01), Datta et al.
Wolf et al., “Silicon Processing for the VLSI Era”, vol. 1, 1986 by Lattice Press, pp. 434-446.

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