Electroetching methods and systems using chemical and...

Electrolysis: processes – compositions used therein – and methods – Electrolytic erosion of a workpiece for shape or surface...

Reexamination Certificate

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C204S22400M, C205S662000

Reexamination Certificate

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06821409

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to semiconductor integrated circuit technology and, more particularly, to an electroetching process and apparatus to yield planar layers.
BACKGROUND OF THE INVENTION
Conventional semiconductor devices generally include a semiconductor substrate, usually a silicon substrate, and a plurality of sequentially formed dielectric interlayers such as silicon dioxide and conductive paths or interconnects made of conductive materials. The interconnects are usually formed by filling a conductive material in trenches etched into the dielectric interlayers. In an integrated circuit, multiple levels of interconnect networks laterally extend with respect to the substrate surface. The interconnects formed in different layers can be electrically connected using vias or contacts. A conductive material filling process of such features, i.e., via openings, trenches, pads or contacts, can be carried out by electrodepositing a conductive material, such as copper, over the substrate including such features. There are many conventional electrodeposition methods and tools that deposit conformal layers of Cu on various substrates.
The importance of overcoming the various deficiencies of the conventional electrodeposition techniques, which deposit conformal coatings, is evidenced by technological developments directed to the deposition of planar copper layers. In such processes, a pad or a mask can be used during at least a portion of the electrodeposition process when there is physical contact or close proximity, and relative motion between the workpiece surface and the pad or the mask. For example, U.S. Pat. No. 6,176,992 to Talieh, entitled “Method and Apparatus for Electrochemical Mechanical Deposition” and commonly owned by the assignee of the present invention, describes in one aspect an electro chemical mechanical deposition technique (ECMD) that achieves deposition of the conductive material into the cavities on the substrate surface while minimizing deposition on the field regions by polishing the field regions with a pad as the conductive material is deposited, thus yielding planar copper deposits.
U.S. application Ser. No. 09/740,701 entitled “Plating Method and Apparatus that Creates a Differential Between Additive Disposed on a Top Surface and a Cavity Surface of a Workpiece Using an External Influence,” also assigned to the same assignee as the present invention, describes in one aspect a method and apparatus for plating a conductive material onto the substrate by creating an external influence to cause a differential in additives to exist for a period of time between a top surface and a cavity surface of a workpiece. While the differential is maintained, power is applied between an anode and the substrate to cause greater relative plating of the cavity surface than the top surface.
U.S. application Ser. No. 09/735,546 entitled “Method and Apparatus For Making Electrical Contact To Wafer Surface for Full-Face Electroplating or Electropolishing,” filed on Dec. 14, 2000 describes in one aspect a technique for providing full face electroplating or electropolishing or electroetching. And U.S. application Ser. No. 09/760,757 entitled “Method and Apparatus for Electrodeposition of Uniform Film with Minimal Edge Exclusion on Substrate,” filed on Jan. 17, 2001 describes in one aspect a technique for forming a flat conductive layer on a semiconductor wafer surface without losing space on the surface for electrical contacts.
After depositing copper into the features on the semiconductor wafer surface using either planar deposition techniques or the conventional techniques, an electropolishing or a chemical mechanical polishing step (CMP) may be employed. These processes planarize the resulting surface, and if continued, the conductive material is removed off the field regions of the surface and left only within the features such as vias, contacts, trenches, bond pads etc. In the electro polishing, which is also referred to as “electrochemical etching” or “electroetching,” both the material to be removed and a conductive electrode are dipped into the electro-polishing solution. Typically an anodic (positive) voltage is applied to the material to be removed with respect to the conductive electrode. With the applied voltage, the material is electrochemically dissolved and removed from the wafer surface.
Also, various other methods and apparatus, which attempt to improve the efficiency of the polishing process by combining electroetching with a CMP process step, exist. For example, U.S. Pat. No. 6,066,030, issued May 23, 2000 to Uzoh et al., generally employs a single device to carry out sequentially both CMP process and electroetching process of a substrate. The device includes a polishing head having a polishing pad and a cathode, which is arranged adjacent the polishing head while the anode is the substrate to be polished and electroetched. The electroetching process requires delivery of an etching or polishing solution to the substrate surface through the cathode while the tool is rotated and/or laterally moved across the substrate. The electroetching step is followed by the CMP process where a polishing slurry is introduced between the polishing pad and the substrate while the substrate is rotated.
To this end, however, there is need for alternative etching techniques that uniformly etches back conductive films. There is also a need for a process that yields planar surfaces.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an apparatus and process that can more efficiently etch a material deposited on a workpiece.
It is an object of the present invention to provide an apparatus and process that can more efficiently etch a metal deposited on a workpiece.
It is a further object of the invention to form at least one intermediate compound from a material layer of a workpiece such that the intermediate compound can be more easily mechanically removed than the material.
It is a still further object of the present invention to provide a method of introducing noncontaminating particulates to an electroetching or chemical mechanical etching process.
The above object of the invention, among others, either taken singly or in combination, are achieved by the method and apparatus according to the present invention. In one aspect the present invention applies an electrochemical etching solution to a material layer, preferably a metal layer, disposed on a workpiece, in the presence of a current. This electrochemical etching solution supplies to the material on the substrate surface the species to form an intermediate compound on the surface that can be more easily mechanically removed as intermediate compound fragments than the material. By removing the intermediate compound fragments, the process allows more efficient use of the supplied current to form another layer of intermediate compound that can also be mechanically removed, rather than using the current to result in another compound on the surface of the material that eventually dissolves into the solution.
Accordingly, raised surface portions of the material layer can be removed more quickly than surface portions within grooves or other cavities on the material layer, thus creating more efficient removal from the raised surface portions.
In another aspect of the invention, such intermediate compound particulates are externally generated and used to mechanically remove the surface layer of the material. Such intermediate particulates do not contaminate, and thus allow for more efficient material removal, as well as plating to occur within the same chamber, if desired.


REFERENCES:
patent: 5766446 (1998-06-01), Spindt et al.
patent: 6451698 (2002-09-01), Au et al.
patent: 6527920 (2003-03-01), Mayer et al.
patent: 2002/0088709 (2002-07-01), Hongo et al.
patent: 2002/0139682 (2002-10-01), Basol et al.

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