Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Depositing predominantly single metal or alloy coating on...
Reexamination Certificate
2001-04-03
2003-02-25
Nguyen, Nam (Department: 1741)
Electrolysis: processes, compositions used therein, and methods
Electrolytic coating
Depositing predominantly single metal or alloy coating on...
C205S123000, C205S125000, C205S920000, C205S646000
Reexamination Certificate
active
06524461
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to electrodeposition of metals and more particularly to electrodeposition of metals into small or microscopic recesses on the surface of a substrate and formation of uniform layers of electrodeposited metal on a substrate.
2. Brief Description of the Prior Art
Electronic devices such as computers, cellular telephones, electronic entertainment devices, and the like, have long been manufactured by mounting components on circuit boards having electrically conductive traces thereon to interconnect the components.
In the manufacture of such electronic equipment, development of technology and economics have driven the industry toward ever-smaller devices, containing ever-increasing numbers of components. At the level of semiconductor devices very large scale integration (VLSI) has produced chips containing up to a few million transistors on a single semiconductor chip no larger than several millimeters on a side. Such chips have conventionally been packaged or encapsulated in small modules having external lead wires for interconnecting the chips. The interconnections have conventionally been provided by circuit boards having electrical conductors prepared by so called “printed wiring” techniques that involve masking, etching, and plating of conductive metal, usually copper, to provide the interconnects between chip modules or sockets designed to hold such modules. These “printed wiring boards” (PWB) have typically been used to interconnect chips of conventional sizes. The chips or socket are mounted on the surface of the board with terminals fitted into holes through the board. The holes are typically lined with a thin layer of copper that is integral with the traces of copper on the surface of the board. The terminals of the chips or sockets are soldered to the copper layer lining the holes and thereby interconnected through the copper traces. The PWBs may have more than one layer of copper traces. Connections between traces in different layers are also provided by copper-lined holes passing through the board, commonly known as plated through-holes (PTHs).
The copper lining in such holes is typically applied electrolytically, by first laying down a thin layer of electroless copper to provide electrical continuity and then electroplating copper to a thickness of a few mils to provide the connecting layer. The holes in the PWBs typically are at least 12-13 mils in diameter. Because of the well-known problem of depositing metal electrolytically in recesses, special techniques have to be used to assure that a uniform layer of conductive metal is deposited in the holes. Consequently conventional techniques to enhance the “throwing power” of the electroplating system have been employed, such as agitation of the bath, addition of certain chemical compounds to the electroplating bath, and/or the use of pulsed current plating.
Although conventional techniques have generally been successful in the manufacture of PWBs having the dimensions that have been commonly used in electronic devices such as television receivers, personal computers, and the like, the trend to ever-smaller equipment such as cellular telephones, more advanced computers, and the like, has led to the necessity of mounting chips closer together in multichip modules (MCMs). Instead of terminals extending into holes in the circuit board, such MCMs frequently have only metallized locations on a major surface of the module to provide interconnections. The semiconductor devices or chips are placed relatively close together on a substrate having holes drilled therein at the locations of the interconnecting pads on the modules. In such boards the holes are typically of smaller diameter than those of conventional PWBs, and may range from about 25 micrometers (1 mil) to about 250 micrometers (10 mils). Such holes are also effectively blind holes, because the semiconductor devices are already mounted to the board, and the conductor deposition step provides the electrical contact to the terminal pads on the semiconductor devices as well as the interconnections between the devices. The use of small chips mounted close together and interconnected by means of conductors deposited in small holes has come to be known as high density interconnect (HDI) technology. With single sided, double sided and multilayers representing the first three generations of PWBs, high density PWBs are also being termed the fourth generation PWB. Other names for this emerging technology includes build up boards and micro via boards.
Deposition of conductive metal into the small, blind holes or vias used in HDI has presented a number of problems. Conventional metallization procedures, such as chemical vapor deposition or physical vapor deposition or electroless plating, are slow and expensive. Electroplating into small blind holes using conventional procedures has not been able to provide a reliable layer of conductive metal in the hole to assure a reliable interconnection of the chips. In particular, conventional electroplating techniques tend to deposit excess metal at the sharp corners at the top or entrance of the hole. Such deposits encroach on the opening of the hole and hinder deposition in the lower portion of the hole. They may even completely block the mouth of the hole leading to voids in the vias or interconnects. Additionally, in some cases it is desirable to obtain a conformal deposit, which is also adversely affected by dogboning at the corners of the vias. Furthermore, chemical additives in the plating bath may lead to inclusions of impurities derived from the plating bath within the metal deposit. Such problems can lead to connections that have a high electrical resistance and are mechanically brittle and unreliable in service. In addition, the use of nonconventional electroplating techniques such as pulse current plating, typically in conjunction with chemical additives, has relied on waveform parameters successfully developed for traditional PWB applications, such as 13 mil and greater PTHs. These waveforms generally operate with long cathodic duty cycles and short anodic duty cycles. This approach has led to similar problems encountered in conventional plating with excess metal deposit at the opening of the via leading to voids in the interconnect or to excessive deposit of metal on the surface of the substrate. In addition to the problems cited above, such nonuniform metallization within the via or between the via and the substrate results in excessive processing time and cost associated with the excess metal.
Similar problems regarding the electrodeposition of metallic conductors are encountered in the manufacture of the semiconductor devices themselves that are mounted on the circuit boards and interconnected by conductive traces.
The manufacture of semiconductor devices, especially very large scale integrated (VLSI) as well as ultra large scale integrated (ULSI) chips is driven by technical and economic considerations toward the production of devices comprising greater numbers of transistors and associated circuits on a single semiconductor chip or wafer. For clarity, VLSI is meant to include both VLSI and ULSI chips. The most complex chips manufactured today have a few million transistors on a semiconductor chip no larger than several millimeters on a side. The electrical interconnections between the transistors in such chips are provided by fine wires of a conductive metal extending in channels formed horizontally and vertically in the body of the chip. Conventionally, these electrical connections have been made of aluminum, which can be deposited through vapor phase deposition techniques such as physical vapor deposition (PVD) and chemical vapor deposition (CVD). However, as the dimensions of the transistors have decreased into the submicron region, the cross sections of the connections have also decreased and the resistance of the connections has increased. In order to reduce the resistance of the connections in VLSI circuits containing devices of submicron d
Sun Jenny J.
Taylor E. Jennings
Zhou Chengdong
Faraday Technology Marketing Group LLC
Nguyen Nam
Nicolas Wesley A.
Vorys Sater Seymour and Pease LLP
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