Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Depositing predominantly single metal or alloy coating on...
Reexamination Certificate
1999-01-29
2001-04-03
Gorgos, Kathryn (Department: 1741)
Electrolysis: processes, compositions used therein, and methods
Electrolytic coating
Depositing predominantly single metal or alloy coating on...
C205S105000, C205S123000
Reexamination Certificate
active
06210555
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to electrodeposition of metals and more particularly to electrodeposition of metals into small recesses on the surface of a substrate.
2. Brief Description of the Prior Art
In the manufacture of electronic equipment, development of technology and economics have driven the industry toward ever-smaller devices, containing ever-increasing numbers of components. At the level of semiconductor devices very large scale integration (VLSI) has produced chips containing up to a few million transistors on a single semiconductor chip no larger than several millimeters on a side. Such chips have conventionally been packaged or encapsulated in small modules having external lead wires for interconnecting the chips. The interconnections have conventionally been provided by circuit boards having electrical conductors prepared by so called “printed wiring” techniques that involve masking, etching, and plating of conductive metal, usually copper, to provide the interconnects between chip modules or sockets designed to hold such modules. These “printed wiring boards” (PWB) have typically been used to interconnect chips of conventional sizes. The chips or socket are mounted on the surface of the board with terminals fitted into holes through the board. The holes are typically lined with a thin layer of copper that is integral with the traces of copper on the surface of the board. The terminals of the chips or sockets are soldered to the copper layer lining the holes and thereby interconnected through the copper traces. The PWBs may have more than one layer of copper traces. Connections between traces in different layers are also provided by copper-lined holes passing through the board, commonly known as plated through-holes (PTHs)
The copper lining in such holes is typically applied electrolytically, by first laying down a thin layer of electroless copper to provide electrical continuity and then electroplating copper to a thickness of a few mils to provide the connecting layer. The holes in the PWBs typically are at least 12-13 mils in diameter. Because of the well-known problem of depositing metal electrolytically in recesses, special techniques have to be used to assure that a uniform layer of conductive metal is deposited in the holes. Consequently conventional techniques to enhance the “throwing power” of the electroplating system have been employed, such as agitation of the bath, addition of certain chemical compounds to the electroplating bath, and/or the use of pulsed current plating.
Although conventional techniques have generally been successful in the manufacture of PWBs having the dimensions that have been commonly used in electronic devices such as television receivers, personal computers, and the like, the trend to ever-smaller equipment such as cellular telephones, more advanced computers, and the like, has led to the necessity of mounting chips closer together in multichip modules (MCMs). Instead of terminals extending into holes in the circuit board, such MCMs frequently have only metallized locations on a major surface of the module to provide interconnections. The semiconductor devices or chips are placed relatively close together on a substrate having holes drilled therein at the locations of the interconnecting pads on the modules. In such boards the holes are typically of smaller diameter than those of conventional PWBs, and may range from about 25 micrometers (1 mil) to about 250 micrometers (10 mils). Such holes are also effectively blind holes, because the semiconductor devices are already mounted to the board, and the conductor deposition step provides the electrical contact to the terminal pads on the semiconductor devices as well as the interconnections between the devices. The use of small chips mounted close together and interconnected by means of conductors deposited in small holes has come to be known as high density interconnect (HDI) technology.
Deposition of conductive metal into the small, blind holes or vias used in HDI has presented a number of problems. Conventional metallization procedures, such as chemical vapor deposition or physical vapor deposition, are slow and expensive. Electroplating into small blind holes using conventional procedures has not been able to provide a reliable layer of conductive metal in the hole to assure a reliable interconnection of the chips. In particular, conventional electroplating techniques tend to deposit excess metal at the sharp corners at the top or entrance of the hole. Such deposits encroach on the opening of the hole and hinder deposition in the lower portion of the hole. They may even completely block the mouth of the hole leading to voids in the vias or interconnects. Furthermore, chemical additives in the plating bath may lead to inclusions of impurities derived from the plating bath within the metal deposit. Such problems can lead to connections that have a high electrical resistance and are mechanically brittle and unreliable in service. In addition, the use of nonconventional electroplating techniques such as pulse current plating, typically in conjunction with chemical additives, has relied on waveform parameters successfully developed for traditional PWB applications, such as 13 mil and greater PTHs. These waveforms generally operate with long cathodic duty cycles and short anodic duty cycles. This approach has led to similar problems encountered in conventional plating with excess metal deposit at the opening of the via leading to voids in the interconnect or to excessive deposit of metal on the surface of the substrate. In addition to the problems cited above, such nonuniform metallization within the via or between the via and the substrate results in excessive processing time and cost associated with the excess metal.
Accordingly, a need has continued to exist for a method of depositing metallic conductors, especially copper, into the blind holes used in high density interconnects for multichip modules and the like.
SUMMARY OF THE INVENTION
The problems encountered in electrodeposition of continuous conductive layers of metals into small blind holes and vias have now been alleviated by the method of this invention, wherein a metal is selectively deposited on a substrate to provide a coating that lines or fills small blind holes and/or recesses without excessive deposition of metal at or near convex portions of the substrate surface such as protuberances and edges. The selective deposition is accomplished by a process in which an electrically conductive substrate having a blind hole or recess with at least one transverse dimension not greater than about 350 micrometers and preferably in a range of from about micrometers to about 350 micrometers is immersed in an electroplating bath containing ions of the metal to be deposited in said recess, and provided with a suitable counterelectrode,
a modulated reversing electric current is passed between the electrodes through the plating bath, which may or may not contain chemical additives to enhance throwing power, having pulses that are cathodic with respect to the substrate and pulses that are anodic with respect to the substrate, the cathodic pulses having a short duty cycle and the anodic pulses having a long duty cycle, the charge transfer ratio of the cathodic pulses to the anodic pulses being greater than one, and the frequency of the pulses ranging from about 10 Hertz to about 5 kilohertz.
Accordingly, it is an object of the invention to provide an electrochemical method for depositing a metal in small blind holes in a substrate.
A further object is to provide a method for selective electrodeposition of a metal on a substrate having small recesses on its surface.
A further object is to provide a method for depositing metal from an electrolytic bath onto a substrate having recesses therein in order to provide reliable electrical connection between the surface of the substrate and the bottom portion of the recess.
A further object is to provide a method for forming a void-free deposit
Sun Jenny J.
Taylor E. Jennings
Zhou Chengdong
Faraday Technology Marketing Group LLC
Gorgos Kathryn
Nicolas Wesley A.
Vorys Sater Seymour and Pease LLP
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