Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Depositing predominantly single metal or alloy coating on...
Reexamination Certificate
2001-10-15
2004-12-07
Wong, Edna (Department: 1753)
Electrolysis: processes, compositions used therein, and methods
Electrolytic coating
Depositing predominantly single metal or alloy coating on...
C205S102000, C205S105000, C205S118000, C205S123000, C205S125000, C205S131000
Reexamination Certificate
active
06827833
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to electrodeposition of metals in deep cavities and more particularly to depositing a uniform layer of metal on the interior surfaces of a recess or hole having a high aspect ratio.
2. Brief Description of the Prior Art
Electronic devices such as computers, cellular telephones, electronic entertainment devices, and the like, have long been manufactured by mounting components on circuit boards having electrically conductive traces thereon to interconnect the components.
In the manufacture of such electronic equipment, development of technology and economics have driven the industry toward ever-smaller devices, containing ever-increasing numbers of components. At the level of semiconductor devices very large scale integration (VLSI) and ultra large scale integration (ULSI), hereafter referred to as simply VLSI, has produced chips containing up to a few million transistors on a single semiconductor chip no larger than several millimeters on a side. Such chips have conventionally been packaged or encapsulated in small modules having external lead wires for interconnecting the chips. The interconnections have conventionally been provided by circuit boards having electrical conductors prepared by so called “printed wiring” techniques that involve masking, etching, and plating of conductive metal, usually copper, to provide the interconnects between chip modules or sockets designed to hold such modules. These “printed wiring boards” (PWB) have typically been used to interconnect chips of conventional sizes. The chips or socket are mounted on the surface of the board with terminals fitted into holes through the board. The holes are typically lined with a thin layer of copper that is integral with the traces of copper on the surface of the board. The terminals of the chips or sockets are soldered to the copper layer lining the holes and thereby interconnected through the copper traces. The PWBs may have copper traces on both sides as well as more than one inner layer of copper traces. Connections between copper traces in the different layers of these double-sided and multilayered PWBs are also provided by copper-lined holes passing through the board, commonly known as plated through-holes (PTHs).
The copper lining in such holes is typically applied electrolytically, by first laying down a thin layer of electroless copper to provide electrical continuity and then electroplating copper to a thickness of a few mils to provide the connecting layer. While the copper could be applied solely using the electroless process, the processing time for the electroless process is significantly greater than the processing time for the electrolytic process. The holes in the PWBs typically are at least 12-13 mils in diameter. Because of the well-known problem of depositing metal electrolytically in recesses, special techniques have to be used to assure that a uniform layer of conductive metal is deposited in the holes. Consequently conventional techniques to enhance the “throwing power” of the electroplating system have been employed, such as agitation of the bath, addition of certain chemical compounds to the electroplating bath, and/or the use of pulsed current plating. Furthermore, while a full-build electroless process can somewhat alleviate the throwing power issue associated with the electrolytic process, the added processing time reduces throughput.
Although conventional techniques have generally been successful in the manufacture of PWBs having the dimensions that have been commonly used in electronic devices such as television receivers, personal computers, and the like, the trend to ever smaller equipment such as cellular telephones, palm computers, portable global positioning devices, more advanced computers, and the like, has led to the necessity of mounting chips closer together in multichip modules (MCMs). Furthermore, the increase in the number of chips mounted on a board has resulted in a corresponding increase in the interconnections. This in turn has required the use of thicker circuit boards having more layers. Consequently, the through-holes and vias that interconnect the layers may become longer and/or deeper without increasing in diameter. The ratio of length to diameter (or to one transverse dimension if the hole or cavity is not of circular cross-section) is commonly referred to as the aspect ratio.
Electroplating of the interior of holes and or recesses in a circuit board has frequently relied on chemical additives to the plating bath that promote uniform deposition of metal. The ability of a bath or component thereof to promote uniform deposition of metal in holes, recesses, and the like has come to be known as “throwing power”.
Additionally, it has been discovered that the use of pulsed current electrolytic waveforms can enhance the plating of metal in the interior of through-holes and the like. In particular, the use of a waveform having a long cathodic pulse followed by a short anodic pulse has been found to be useful in plating the interior surfaces of holes of conventional circuit boards having holes larger than about 325 micrometers (13 mils), having an aspect ratio, i.e., the ratio of the length the hole to the diameter thereof, of about 4:1. It has also been found that when such a waveform is used uniform plating may be achieved even when conventional additives such as levelers and brighteners are omitted from the bath.
In some circuit boards intended for use with small devices such as cellular telephones, hand-held computers and the like, wherein the chips are placed very close together, the holes are typically of smaller diameter than those of conventional PWBs, and may range from about 25 micrometers (1 mil) to about 250 micrometers (10 mils). Such holes are also effectively blind holes and the conductor deposition step provides the electrical contact to the terminal pads on the semiconductor devices as well as the interconnections between the devices. The use of small chips mounted close together and interconnected by means of conductors deposited in small holes has come to be known as high density interconnect (HDI) technology. Plating of such small through-holes and vias has presented problems in achieving uniform deposition of metal both on the surface of the board and within the holes and vias. An effective method of plating such holes using defined pulse waveforms has been disclosed in U.S. Pat. No. 6,210,555, to Taylor et al., as well as in copending U.S. patent application Ser. No. 09/172,299, filed Oct. 14, 1998, copending application Ser. No. 09/553,616, filed Apr. 20, 2000, copending application Ser. No. 09/419,881, filed Oct. 18, 1999, copending application Ser. No. 09/823,749, filed Apr. 03, 2001, and copending application Ser. No. 09/824,663, filed Apr. 04, 2001, the entire disclosures of which are incorporated herein by reference.
As discussed therein, surfaces located within small recesses, cavities and holes can be hydrodynamically inaccessible to the supply of ionically dissolved metals within the plating bath and require defined waveforms to achieve uniform deposition.
However, it has now been found that through-holes and cavities of the dimensions found in conventional circuit boards, i.e., having diameters of about 325 micrometers or greater, but also having aspect ratios greater than about 4:1, are difficult to plate uniformly using the waveforms conventionally applied to holes of such diameter. The problem is especially severe for through-holes that are being used or have been proposed for certain circuit boards wherein the through-holes have aspect ratios of 10:1, 15:1, or even 20:1 or greater. When circuit boards having such through-holes are plated, the metal, e.g., copper, tends to be deposited preferentially near the mouth of the holes. The central region of the holes, i.e., the region approximately equidistant from either surface of the board tends to receive a thinner deposit of metal, i.e., be lightly plated, or, in extreme cases, to receive no metal at all. A
Sun Jenny J.
Taylor E. Jennings
Faraday Technology Marketing Group LLC
Mutschler Brian L.
Thompson Hine LLP
Wong Edna
LandOfFree
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