Electric lamp or space discharge component or device manufacturi – Process – With assembly or disassembly
Reexamination Certificate
2001-03-22
2003-05-27
Ramsey, Kenneth J. (Department: 2879)
Electric lamp or space discharge component or device manufacturi
Process
With assembly or disassembly
Reexamination Certificate
active
06568978
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an electrode substrate including a transparent conductive layer which is in contact with both an inorganic insulating region formed of an inorganic insulating layer and an organic insulating region formed of an organic insulating layer, a method for producing the same, and a display device including the same.
2. Description of the Related Art
A transparent conductive layer including ITO (indium tin oxide) is usable as an electrode for allowing light to transmit therethrough and controlling light transmission. Attempts have been made to practically use an electrode substrate having such a transparent conductive layer in, for example, display devices including electroluminescence display devices, touch panels, and solar cells.
An exemplary display device including an electrode substrate having a transparent conductive layer both on an organic insulating layer and an inorganic insulating layer is a liquid crystal display device. A liquid crystal display device is now actively studied as a type of flat panel display for replacing a CRT display. The liquid crystal display device has already been practically used in a battery-driven super-compact TV, a notebook computer or the like. Hereinafter, a liquid crystal display device including an electrode substrate including a transparent conductive layer provided on both an organic insulating layer and an inorganic insulating layer will be described.
FIG. 1
schematically shows a basic structure of a liquid crystal display device
100
. The liquid crystal display device
100
is of an active matrix TFT array type, using thin film transistors (TFT) as switching devices. Such a type of display device is advantageous to provide a high quality display.
As shown in
FIG. 1
, the liquid crystal display device
100
includes an upper substrate
102
, a lower substrate
101
as an electrode substrate, and a liquid crystal layer
109
interposed between the upper substrate
102
and the lower substrate
101
. Liquid crystal molecules in the liquid crystal layer
109
are controlled by the upper substrate
102
and the lower substrate
101
.
The lower substrate
101
includes an insulating plate
20
; and a plurality of gate lines
105
, a plurality of source lines
106
, a plurality of pixel electrodes
103
, and a plurality of TFTs
108
respectively provided in correspondence with the plurality of pixel electrodes
103
, which are provided on the insulating plate
20
. The plurality of pixel electrodes
103
are each connected to the corresponding gate line
105
and the corresponding source line
106
through the corresponding TFT
108
.
FIG. 2
is a plan view of the lower substrate
101
. The planar region of the lower substrate
101
includes a display region
150
(hatched in
FIG. 2
) and a peripheral region
160
. The display region
150
includes the plurality of pixel electrodes
103
and the plurality of TFTs
108
for controlling the pixel electrodes
103
connected thereto. The pixel electrodes
103
are each formed of a transparent conductive layer. Since the liquid crystal display device
100
(
FIG. 1
) is of a transmission type, at least a part of the insulating plate
20
is formed of a transparent material, and the pixel electrodes
103
are formed of a transparent conductive material, so that an image is displayed using light (generally, light from a light source) passing to the display side from the side opposite to the display side of the liquid crystal display device
100
. In this manner, the light is transmitted and controlled. The liquid crystal display device
100
(
FIG. 1
) is of a transparent type, but the description here is applicable to a transmission region of a liquid crystal display device of a transmission/reflection type.
The peripheral region
160
includes a plurality of gate connection terminals
110
, a plurality of source connection terminals
120
, and a plurality of common connection terminals
130
. The plurality of gate connection terminals
110
are respectively connected to the plurality of gate lines
105
; the plurality of source connection terminals
120
are respectively connected to the plurality of source lines
106
; and the plurality of common connection terminals
130
are respectively connected to a plurality of common lines
107
. The gate lines
105
, the source lines
106
and the common lines
107
are provided in the peripheral region
160
and extend to the display region
150
. In this specification, each gate connection terminal
110
and the vicinity thereof will be referred to as a “gate connection terminal area
111
”, each source connection terminal
120
and the vicinity thereof will be referred to as a “source connection terminal area
121
”, and each common connection terminal
130
and the vicinity thereof will be referred to as a “common connection terminal area
131
”. The gate connection terminal areas
111
, source connection terminal areas
121
and the common connection terminal area
131
will be collectively referred to as a “peripheral terminal area”.
FIG. 3
is an enlarged plan view of the display region
150
of the lower substrate
101
. One pixel electrode
103
is indicated by a dashed line in FIG.
3
. The gate lines
105
and the common lines
107
are provided parallel to each other, and the source lines
106
are provided perpendicular to the gate lines
105
and the common lines
107
. In the vicinity of an intersection of each gate line
105
and each source line
106
, the gate line
105
is branched to be connected to a gate electrode of the TFT
108
, and the source line
106
is branched to be connected to a source electrode of the TFT
108
. A connection electrode
48
which is connected to a drain electrode of the TFT
108
is provided to partially overlap the corresponding common line
107
. An area in which the connection electrode
48
and the common line
107
overlap each other has a contact hole
50
.
FIG. 4
is a cross-sectional view of the display region
150
of the substrate
101
along line A-A′ in FIG.
3
. In
FIG. 4
, the area including the gate line
105
and the vicinity thereof will be referred to as a “TFT area”, and the area including the common electrode
107
and the vicinity thereof will be referred to as a “contact hole area”.
In the TFT area, the gate line
105
(more specifically, the branched portion of the gate line
105
) is provided on the insulating plate
20
. A gate insulating layer
44
is provided on the insulating plate
20
so as to cover the gate line
105
. The gate insulating layer
44
can be formed of silicon nitride (SiN
x
). An amorphous semiconductor layer
45
is provided on the gate insulating layer
44
, and the source electrode
46
a
and the drain electrode
46
b
of the TFT
108
are provided on the amorphous semiconductor layer
45
with a gap interposed therebetween. As described above, the source electrode
46
a
is connected to the source line
106
, and the drain electrode
46
b
is connected to the connection electrode
48
. The TFT
108
including the above-described elements is covered with an organic insulating layer
49
formed of a transparent material. The organic insulating layer
49
has a flat top face, and the pixel electrode
103
is provided on the organic insulating layer
49
.
In the contact area, the common electrode
107
is provided on the insulating plate
20
, and the gate insulating layer
44
is provided on the insulating plate
20
so as to cover the common electrode
107
. The gate insulating layer
44
is covered with the connection electrode
48
. The gate insulating layer
44
is covered with the organic insulating layer
49
. The pixel electrode
103
is provided on the organic insulating layer
49
. The contact hole
50
is provided so that the connection electrode
48
and the pixel electrode
103
are in direct contact with each other.
The above-described structure of the display region
150
provides a high numerical aperture mainly for the following two reasons. (1) Si
Fujikawa Takashi
Kataoka Yoshiharu
Kokura Masafumi
Nixon & Vanderhye P.C.
Ramsey Kenneth J.
Sharp Kabushiki Kaisha
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