Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads
Reexamination Certificate
2001-05-03
2004-07-20
Zarneke, David A. (Department: 2829)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Bump leads
C257S779000
Reexamination Certificate
active
06765293
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an electrode structure of a semiconductor device for solder-bonding to a main substrate.
2. Description of the Related Arts
In order to make personal home electric appliances such as a portable telephone, a video camera, and a personal computer small, compact, lightweight, the package of a semiconductor device has been changed from an LSI package having a gull-wing type lead electrode to a BGA (ball grid array) type or a CSP (chip scale package) type which are compact, lightweight packages.
FIG. 5
is an outward view of a BGA type package semiconductor device, and (a) is a side view and (b) is a bottom view.
FIG. 6
is a partial side view of a state where the BGA type package semiconductor device of
FIG. 5
is bonded to a main substrate. The semiconductor element which is mounted to a carrier substrate
502
and is not shown in the drawing is sealed in a package composed of a resin part
501
and the carrier substrate
502
, and an external terminal of the semiconductor element is connected to an external part via a soldering land
503
that is an electrode grid-like arranged on the carrier substrate
502
. A soldering land
602
is provided at a position corresponding to the soldering land
503
of the carrier substrate
502
of the semiconductor device in the main substrate
601
in which the semiconductor device is mounted and is bonded to the soldering land
503
of the semiconductor substrate via solder
603
. Both soldering land
503
and soldering land
602
have cylindrical shapes with low heights, their upper faces are generally smooth flat faces, and the smooth upper faces of both lands are bonded across the solder
603
.
The interval of the lands becomes narrow and the areas of lands become small with miniaturization of a package, and thus a problem that the joint strength and the reliability of the lands by means of the solder become low has occurred.
It is an object of the present invention to provide an electrode structure of a carrier substrate of a semiconductor device in which the strength and the reliability of the joint portion between an electrode of a semiconductor package and an electrode of a main substrate are improved.
SUMMARY OF THE INVENTION
An electrode structure of a carrier substrate of a semiconductor device of the present invention is an electrode structure of a carrier substrate of a semiconductor device for solder-bonding the semiconductor device to a main substrate, wherein a recess is formed in a central area of the electrode, and the electrode has a through portion passing through between the recess and an outer portion of a circumferential wall surface surrounding the recess of the central area, on the circumferential wall surface.
The electrode may be hemispheric having a flange portion and has a concentric hemispheric face hollow portion thereinside, the hemispheric portion of the electrode may be fitted into a hemispheric recess provided on an outer surface in the carrier substrate of the semiconductor device, and the electrode may be fixedly attached to the carrier substrate so that the flange portion abuts the outer surface of the carrier substrate. The through portion passing through between the recess and the outer portion of the wall surface may be at least one slit provided in the flange portion and the wall surface of the electrode adjacent to the flange portion.
The electrode may be cylindrical having a flange portion and has a concentric cylindrical hollow portion thereinside, the cylindrical portion of the electrode may be fitted into a cylindrical recess provided on an outer surface in the carrier substrate of the semiconductor device, and the electrode may be fixedly attached to the carrier substrate so that the flange portion abuts the outer surface of the carrier substrate. The through portion passing through between the recess and the outer portion of the wall surface may be at least one slit provided in the flange portion and the cylindrical wall surface of the electrode adjacent to the flange portion to a position close to a bottom.
The package of the semiconductor device may be of a BGA type or a CSP type.
By forming a recess in a central area of the electrode, a joint area between a soldering land and solder increases, and the joint is three-dimensional. Further, since a through portion connecting the recess and the outer portion of the wall surface is provided, the air thereinside escapes, and solder becomes wet and spreads in the recess fully, whereby the same strength joint can be achieved by a small amount of solder and the interval between the carrier substrate and the main substrate can be narrowed
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John H. Lau, “Chip Scale Package”, 1999, McGraw-Hill.
Geyer Scott B.
NEC Corporation
Young & Thompson
Zarneke David A.
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