Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2001-11-19
2004-11-09
Fourson, George (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S753000, C257S762000, C257S766000, C257S774000
Reexamination Certificate
active
06815818
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor chips and integrated circuits, and more particularly to an electrode structure for use in integrated circuits, such as electronic systems, memory systems and the like.
BACKGROUND OF THE INVENTION
In fabricating integrated circuits, semiconductor chips and the like, chemical/mechanical planarization can be used as an intermediate operation to planarize a structure to provide a uniform, level surface for subsequent processing operations in the manufacturing of a semiconductor chip or integrated circuit. For example, electrodes or electrical contacts between different layers of conductive materials in a semiconductor chip can be formed by depositing a first layer of conductive material, typically a metal, although a semiconductor material could be used as well, and then depositing a thin dielectric layer over the first conductive layer. The dielectric layer is then patterned to form at least one opening in the dielectric layer to expose a portion of the surface of the first conductive layer. The opening can have a small aspect ratio of depth to width. For instance, the opening can be about half a micron wide but only about 500 angstroms deep thus presenting a aspect ratio of about 0.1. A second layer of a different conductive material is then deposited on the dielectric layer and in the opening on the first conductive layer to make electrical contact through the opening with the first conductive layer. The second conductive layer is then removed form the dielectric layer or planarized to expose the dielectric layer and to form an isolated electrode or damascene contact structure in the opening before subsequent fabrication operations. In removing the second conductive layer by chemical/mechanical processing or planarization (CMP), the forces created by the CMP process can have a tendency to force the conductive material of the second layer out of the opening thereby destroying the contact.
Accordingly, for the reason stated above, and for other reasons that will become apparent upon reading and understanding the present specification, there is a need for an electrode structure and method of fabrication that provides substantially improved adhesion between a first layer of conductive material and second layer of a different conductive material, particularly during a CMP operation, and that does not adversely effect the conductivity between the two layers or create an electrical barrier. There is also a need for a method of fabricating an electrode structure that does not effect or damage other components that may already have been formed on the same wafer or substrate and that does not adversely effect the manufacturing process by requiring a significant number of additional process operations.
SUMMARY OF THE INVENTION
The above mentioned problems with electrode structures are addressed by the present invention and will be understood by reading and studying the following specification. Electrode structures, memory cells and systems are provided by the present invention that exhibit good adhesion between different conductive layers during manufacturing operations such as CMP without the conductivity between the layers being adversely effected. Methods of fabricating are also provided by the present invention that do not adversely effect other components that may have already been formed on a semiconductor die.
In accordance with the present invention, an electrode structure includes a first layer of conductive material and a dielectric layer formed on a surface of the first layer. An opening is formed in the dielectric layer to expose a portion of the surface of the first layer. A binding layer is formed on the dielectric layer and on the exposed portion of the surface of the first layer and a second layer of conductive material is formed on the conductive binding layer.
In accordance with an embodiment of the present invention, a memory cell, includes a first layer of conductive material and a dielectric layer formed on a surface of the first layer. An opening is formed in the dielectric layer to expose a portion of the surface of the first layer. A binding layer is formed on the dielectric layer and on the exposed portion of the surface of the first layer and a second layer of conductive material is formed on the binding layer. A layer of doped chalcogenide material is formed on the second layer of conductive material and a third layer of conductive material is formed on the layer of doped chalcogenide material.
In accordance with another embodiment of the present invention, a method of making an electrode, comprises: forming a first layer of conductive material; forming a dielectric layer on a surface of the first layer; forming an opening in the dielectric layer to expose a portion of the surface of the first layer; forming a binding layer on the dielectric layer and on the exposed portion of the surface of the first layer; and forming a second layer of conductive material on the binding layer. The electrode structure can be annealed at a selected temperature for a predetermined time period to cause conductive material from the second layer to be diffused into the binding layer to improve adhesion and conductivity between the first and second conductive layers.
In accordance with another embodiment of the present invention, a method of making a memory cell, comprises: forming a first layer of conductive material; forming a dielectric layer on a surface of the first layer; forming an opening in the dielectric layer to expose a portion of the surface of the first layer; forming a binding layer on the dielectric layer and on the exposed portion of the surface of the first layer; forming a second layer of conductive material on the binding layer; forming a layer of doped chalcogenide material on the second layer of conductive material; and forming a third layer of conductive material on the layer of doped chalcogenide material. The layer of chalcogenide material can be doped by annealing the memory cell to cause conductive material from the third layer to be chemisorbed into the chalcogenide layer.
These and other embodiments, aspects, advantages and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.
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Pham Thanh V
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