Electrode forming method and field effect transistor

Details Electrode forming method and field effect transistor Electrode forming method and field effect transistor

2002-12-10

2004-12-28

Ngô, Ngân V. (Department: 2814)

Semiconductor device manufacturing: process

Forming schottky junction

Compound semiconductor

C438S638000, C438S642000

Reexamination Certificate

active

06835635

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an electrode forming method and a field effect transistor having a gate electrode formed by the method, and more particularly, to a method for forming a microelectrode.
2. Description of the Related Art
Japanese Unexamined Patent Application Publication No. 8-115923 discloses a conventional method, which is relevant to the present invention, for fabricating a field effect transistor, and in particular, a method for forming a gate electrode.
FIGS. 4A
to
4
G are cross-sectional views schematically illustrating a sequence of typical process steps included in the gate-electrode-forming method disclosed in the publication.
As shown in
FIG. 4A
, a first resist layer
2
is formed on a semiconductor substrate
1
, and is patterned so as to form a first opening
3
.
Next, as shown in
FIG. 4B
, a first conductor layer
4
, which contains a high-melting-point metal, such as WSi, is formed by sputtering so as to cover the first resist layer
2
.
Subsequently, as shown in
FIG. 4C
, a second resist layer
5
is formed so as to cover the first conductor layer
4
, and is patterned so as to form a second opening
6
. The second opening
6
has an area larger than the first opening
3
described above.
Next, as shown in
FIG. 4D
, a second conductor layer
7
, which contains low-resistance metal, such as Au, is formed by electron beam deposition or the like. The second conductor layer
7
is formed on the second resist layer
5
as well as on the first conductor layer
4
in the second opening
6
.
Thereafter, as shown in
FIG. 4E
, the second resist layer
5
is partially removed by etching with O
2
plasma
8
, such that the conductor layer
4
is partially exposed.
Next, as shown in
FIG. 4F
, the first conductor layer
4
is partially removed by dry etching with O
2
/CF
4
plasma
9
. Consequently, a portion that provides a gate electrode
10
(see
FIG. 4G
) in the first conductor layer
4
is separated from the other portions.
Subsequently, as shown in
FIG. 4G
, the first resist layer
2
, the first conductor layer
4
that lies thereon, the second resist layer
5
, and the second conductor layer
7
are removed by a lift-off process. As a result, the gate electrode
10
remains on the semiconductor substrate
11
.
The above-described method for forming the gate electrode
10
shown in
FIGS. 4A
to
4
G employs a lift-off process for removing the first resist layer
2
. In general, to accomplish a lift-off process in appropriate processing time for an industrial purpose, the thickness of the resist layer needs to be at least about several hundred nm, and preferably, about 1 &mgr;m or more.
Meanwhile, to improve the operational speed of a field effect transistor, the gate length must be reduced; in particular, a field effect transistor for use in a millimeter wave band needs to have a gate length of 0.1 &mgr;m or less.
In such a known method, for example, in the formation of the gate electrode
10
having a gate length of 0.1 &mgr;m using the conventional method shown in
FIGS. 4A
to
4
G, when the thickness of the first resist layer
2
is set to 500 nm in consideration of an industrially reliable lift-off process, the cross-sectional shape of the first opening
3
, shown in
FIG. 4A
, inevitably becomes a groove that is significantly narrow and deep, as shown in FIG.
5
A.
Thus, when the process illustrated in
FIG. 4B
is performed to deposit a metal thin film that provides the first conductor layer
4
, the width of the first opening
3
decreases, as shown in
FIG. 5B
, as the metal thin film is deposited, thereby causing “constriction” to occur. This makes it difficult to provide sufficient thickness necessary for the first conductor layer
1
within the first opening
3
.
Another possible approach is, as shown in
FIG. 6
, to heat-treat the first resist layer
2
at a temperature of 200° C. such that the edges of the open end of the first opening
3
are thermally deformed and chamfered. Such a process can increase the width of the open end of the first opening
3
, which thus can overcome the problem illustrated in FIG.
5
B.
With such an approach, however, the resist contained in the first resist layer
2
hardens, which makes it significantly more difficult to perform a subsequent lift-off process.
Accordingly, while the conventional method illustrated in
FIGS. 4A
to
4
G can be applied to the formation of the gate electrode
10
having a gate length of, for example, about 0.5 &mgr;m, which is used in a microwave band or the like, it is difficult to apply the conventional method to the formation of the gate electrode
10
having a gate length of 0.1 &mgr;m or sub-0.1 &mgr;m which is suitable for millimeter wave bands.
While the above description has been given for the formation of a gate electrode for a field effect transistor, the same method is generally applicable to the formation of any electrode that has a structure with at least two layers and that involves micro wiring in other semiconductor devices or electronic components.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides an electrode forming method and a field effect transistor having a gate electrode formed by the method, which can overcome the foregoing problems.
The present invention is first directed to a method for forming on a substrate an electrode having a structure with at least two layers. To overcome the above-described technical difficulties, the method for forming the electrode according to the present invention has the following configuration.
That is, a first aspect of the present invention provides a method for forming on a substrate an electrode having a structure with at least two layers. The method includes a first step of forming a first resist layer, which has a first opening therein, on the substrate; a second step of forming a second resist layer on the first resist layer; and a third step of forming a second opening in the second resist layer. The second opening has a larger area than the first opening and is located in the vicinity of the first opening. The method further includes a fourth step of forming a first conductor layer on the inner surfaces of the first and second openings and on surfaces of the first and second resist layers, a fifth step of forming a second conductor layer on the first conductor layer in a region other than the inner peripheral surface of the second opening. The method further includes a sixth step of removing, by etching, the first conductor layer that lies at a portion that is not covered by the second conductor layer within the second opening; a seventh step of removing, by a lift-off process, the second resist layer and the first and second conductor layers which are above the second resist layer; and an eighth step of removing the first resist layer by ashing.
More specifically, the method according to the first aspect of the present invention has the following variations.
Advantageously, in the first step, the first opening may be formed in the first resist layer by using a photolithography technique.
Advantageously, in the third step, the second opening may be formed in the second resist layer by using a photolithography technique.
Advantageously, in the third step, the second opening may be formed to have an inverted-tapered shape in cross-section. With this arrangement, it is possible to prevent the second conductor layer from being formed on the inner peripheral surface of the second opening. Thus, in the sixth step of removing the first conductor layer within the second opening by etching, it is possible to prevent the second layer from interrupting the removal of the first conductor layer.
In the fourth step, the first conductor layer may be formed by sputtering.
Advantageously, in the fifth step, the second conductor layer may be formed by deposition.
Advantageously, in the sixth step, the first conductor layer may be removed by plasma etching with a gas mixture of CF
4
or CHF
3
and oxygen.
The first conductor layer may be formed by sputteri

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