Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material
Reexamination Certificate
2001-08-20
2003-10-28
Dang, Phuc T. (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
C438S124000, C438S613000
Reexamination Certificate
active
06638840
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Technical Field
This invention relates to the field of semiconductor processing, and more particularly, to an electrode contact structure used for connecting to a substrate or wafer during electroplating
(2) Description of the Prior Art
The uniformity of depositing a metal layer onto wafer surfaces by electroplating is directly related to the contact resistance between a thin metal seed layer previously sputtered, and a cathode electrode.
In recent years, escalating requirements for high density and high performance have created the need for improved thickness uniformity.
There are considerable difficulties in the electroplating process in the context of a semiconductor substrate, including undesirable electroplating on the contact fingers, thereby generating contaminating particles, and unwanted electro-deposition of metal on the backside and edges of the substrate.
The following documents relate to various electroplating tools and processes.
U.S. Pat. No. 5,833,820 issued Nov. 10, 1998 to Valery Dubin discloses a tilt angle contact to a wafer in a plating tool.
U.S. Pat. No. 6,132,587 issued to Jome at al.; U.S. Pat. No. 6,108,172 issued to Hagen; U.S. Pat. No. 6,077,412 issued to Ting et al; and U.S. Pat. No. 4,389,296 issued to Seyffert et al., show various plating tools and processes.
BACKGROUND OF THE RELATED ART
The present invention is concerned with conformal contact with a substrate to tolerate dimension variation of the plated substrate.
In the manufacture of devices on a semiconductor wafer, it is now the practice to fabricate multiple levels of conductive (typically metal) layers above a substrate. The multiple metallization layers are employed in order to accommodate higher densities as device dimensions shrink well below one micron design rules. The size of interconnect structures will shrink correspondingly in order to accommodate the overall smaller dimensions. Thus, as integrated circuit technology advances into the sub-0.25 micron range, more advanced metallization techniques are needed to provide improvements over existing practices.
In order to fabricate features, circuits and devices on a substrate, such as a semiconductor wafer, various techniques are used to deposit and etch materials on the wafer. Deposition techniques include processes such as PVD, CVD, sputtering and immersion of the wafer in an electrolyte. The last technique can be used for either electroless deposition or electroplating.
In an electroplating technique, applicable to the current invention, the cells are tanks with sides and a bottom with a drain port on the bottom surface and an opening at the top which permits the substrate to be fully immersed in the electrolytic solution. The cell also includes a sealable top, or lid, per se, to hold the wafer in place and contain the electrolytic solution during immersion and/or inversion, minimizing leakage of the solution during the electroplating process. Once the substrate is immersed in an electrolyte, it is positioned in an electric field between a cathode and an anode, in which charged particles are deposited onto the surface of the substrate or wafer.
The present invention addresses the electroplating technique, in which a material is deposited on a substrate. The technique is implemented with a novel, contact electrode with a tilt angle permitting the described technique to be employed for the mass production of semiconductor products while eliminating some of the major manufacturing problems inherent in the process.
The current electroplating structures are limited by large area penalty and considerable backside and edge contamination problems.
There are many difficulties in the electroplating process in the context of a semiconductor substrate. Specifically, during electroplating, metallic fingers are used to provide electrical contact with a seed layer on a substrate. During the electroplating, metal from the electroplating solution is electroplated on the contact fingers, generating contaminating particles when the electroplated metal is delaminated from the contact fingers. In addition, electroplated metal on the contact fingers leads to increased contact resistance and can result in a high voltage drop and failure.
Another problem frequently encountered electroplating a metal on a substrate is the undesirable electro-deposition of metal on the backside and on the edges of the substrate.
SUMMARY OF THE INVENTION
This invention describes a device for a contact electrode with a tilt angle edge to tolerate dimension variations in the plated material.
An object of the tilt angle edged contact electrode structure is to allow for less area penalty when electroplating a metal on a substrate.
Another object of the invention is to offer a method to prevent metal plating on contacts during electroplating thereby reducing particulate contamination and improving thickness uniformity, and thus, performance.
Yet another object of the invention is the reduction in the possibility of backside and edge contamination during the process of plating metal on the front side of a substrate by preventing electro-deposition of metal on the backside and edges of the substrate.
Still another object of the invention is to provide for personalization of the electroplating process, thereby expanding both the limits and the customization capabilities of the electroplating process for many applications that current devices cannot accommodate.
When used in conjunction with photo resist, the invention expands the limits of the electroplating process and allows for personalization of the process for applications with special needs or inherent difficulties. A typical process includes:
(1) coating the substrate with a photo resist to limit or to personalize the electroplating.
(2) drying the photo resist.
(3) spray rinsing the edge of the wafer, with a photo resist solvent, to remove resist from the edge area, thereby, establishing a contact surface for the electrode.
(4) exposing and developing the photo resist for electroplating.
REFERENCES:
patent: 6140155 (2000-10-01), Mihara et al.
patent: 6372081 (2002-04-01), Uzoh et al.
Ackerman Stephen B.
Dang Phuc T.
Megic Corporation
Saile George O.
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