Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Controlling current distribution within bath
Reexamination Certificate
2002-04-04
2004-06-29
Nicolas, Wesley A. (Department: 1742)
Electrolysis: processes, compositions used therein, and methods
Electrolytic coating
Controlling current distribution within bath
C205S123000, C205S125000, C205S157000, C204S22400M, C204SDIG007
Reexamination Certificate
active
06755954
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains to the field of reactors and methods for electrochemically treating integrated circuit substrates, and in particular, to the shaping of electric fields to control electric current density on substrates during electrochemical treatment.
BACKGROUND OF THE INVENTION
Statement of the Problem
A crucial component of integrated circuits is the wiring or metalization layer that interconnects the individual circuits. Wiring layers have traditionally been made of aluminum and a plurality of other metal layers that are compatible with the aluminum. In 1997, IBM introduced technology that facilitated a transition from aluminum to copper wiring layers. The transition from aluminum to copper required a change in process architecture (to damascene and dual-damascene), as well as a whole new set of process technologies. Copper damascene circuits are produced by initially forming trenches and other embedded features in a wafer, as needed for circuit architecture. These trenches and embedded features are formed by conventional photolithographic processes. Usually, a barrier layer, e.g., of tantalum or tantalum nitride, is formed on silicon oxide in the embedded features. Then, an initial “seed”, or “strike”, layer of copper about 1250 Å thick is deposited by a conventional vapor deposition technique. The seed layer should have good overall wafer uniformity, good step coverage (in particular, a continuous layer of metal deposited onto and conforming to the side-walls of an embedded structure), and minimal closure or “necking” of the top of the embedded feature. See, for example, “Factors Influencing Damascene Feature Fill Using Copper PVD and Electroplating”, Reid, J. et al.,
Solid State Technology
, July 2000, p. 86.
The seed layer is used as a base layer to conduct current for electroplating thicker films. In plating operations, the seed layer functions initially as the cathode of the electroplating cell to carry the electrical plating current from the edge zone of the wafer, where electrical contact is made, to the center of the wafer, including through embedded structures, trenches and vias. The final thicker film electrodeposited on the seed layer should completely fill the embedded structures, and it should have a uniform thickness across the surface of the wafer. Generally, in electroplating processes, the thickness profile of the deposited metal is controlled to be as uniform is possible. This uniform profile is advantageous in subsequent etch-back or polish removal steps.
Any change in conditions that increases the seed layer's resistivity or the seed layer's electrical path will exacerbate the difficulty of achieving a uniform current distribution, which is necessary for effective global electrofilling and uniformity. A number of industry trends, however, tend to increase the seed layer resistivity. These include 1) thinner seed layers, 2) larger diameter wafers, 3) increased pattern density and 4) increased feature aspect ratio (“AR”). Unfortunately, these trends produce challenging conditions for electrofilling, and are not generally amenable to maintaining uniform current density across a wafer. For example, for a given PVD seed deposition condition, smaller features are substantially more “necked” as compared to larger features. As the feature size shrinks, the fixed necking amount becomes relatively more restrictive of the etched feature opening. This effect causes the effective aspect ratio (that is, the AR of the feature into which the plating process must begin plating) of the smaller width features to be substantially higher than that of the original, unseeded etched feature. In order to minimize the necking effect, a thinner seed layer with more conformal side wall coverage is desirable. However, a thinner seed layer causes the initial current distribution across the wafer to become more non-uniform, which (if left uncompensated) leads to poor electrofilling uniformity across the wafer. The seed layer initially causes significant resistance radially from the edge to the center of the wafer because the seed layer is thin. This resistance causes a corresponding potential drop from the edge where electrical contact is made to the center of the wafer. Thus, the seed layer has a nonuniform initial potential that is more negative at the edge of the wafer. The associated deposition rate tends to be greater at the wafer edge relative to the interior of the wafer. This effect is known as the “terminal effect”.
Thus, industry trends create a need for increasingly thinner seed layers having uniform thickness. It is anticipated that in the near future, seed-layer thickness will decrease to below 500 Å, and may eventually decrease to as little as 100 Å. Decreased seed layer thicknesses, combined with increased wafer diameters, however, require improvements in hardware and methods to maintain uniform electroplating.
Various studies have shown the importance of thin seed-layer properties, feature aspect ratio, and feature density on initial plating uniformity. U.S. Pat. No. 6,027,631, issued Feb. 22, 2000, to Broadbent et al., which is hereby incorporated by reference, teaches using asymmetrical shields to influence plating current.
U.S. Pat. No. 6,132,587, issued Oct. 17, 2000, to Jorne et al., teach various methods of mitigating the terminal effect and improving the uniformity of metal electroplating over the entire wafer, including increasing the resistance of the electrolyte, increasing the distance between the wafer and the anode, increasing the thickness of the seed layer, increasing the ionic resistance of a porous separator placed between the wafer and the anode, placement of a rotating distributor in front of the wafer, and establishing contacts at the center of the wafer. Jorne et al. disclose a “rotating distributor jet” that directs different amounts of flow to different radii of a wafer. Creating a spatially varying flowrate at the wafer to influence the global current distribution is practically difficult because the conditions of plating locally vary (flowrate, replenishment of additives, etc.) and, therefore, create a difficult-to-separate convolution between electrofilling and uniformity. Futhermore, no practical means of controlling plating conditions with respect to process time and film thickness was disclosed.
A general approach has been discussed of using a highly electrically resistive membrane placed in close proximity to the wafer so as to establish a “thin resistive plating” region where the potential drop across the wafer will be always smaller than the system potential drop. While this approach might work theoretically, in practice there are a number of problems. Firstly, placing the membrane close to the wafer is difficult (distance between membrane and wafer is typically about 1 cm or less for a typical copper acid plating bath having a conductivity of about 500 ohm
−1
cm
−1
). Secondly, the potential drop and, therefore, the required power increase greatly. Also, establishing uniform flow to the wafer is difficult with a highly restrictive membrane so close to the wafer. That is, it is hard to decouple the fluid flow and the electric field problems because the membrane does not only resist current flow, but also resists fluid flow that needs to be directed at the wafer to replenish consumed reactants.
The ability to successfully electrofill (i.e. the ability to electroplate very small, high AR features without voids or seams) is dependent on a number of parameters. Among these are the 1) plating chemistry, 2) feature shape, width, depth, and density, 3) local seed layer thickness, 4) local seed layer coverage, and 5) local plating current. Items 3-5 are interrelated. As an example of this convolution, a decrease in seed-layer thickness can lead to greater potential differences between the center and edge of a wafer, and hence larger variations in current density during plating. Additionally, it is known that poor seed layer side-wall coverage leads to higher averag
Cleary Timothy Patrick
Janicki Michael John
Mayer Steven T.
Minshall Edmund B.
Ponnuswamy Thomas A.
Nicolas Wesley A.
Novellus Systems Inc.
Patton & Boggs LLP
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