Abrading – Abrading process – Glass or stone abrading
Reexamination Certificate
2000-01-26
2002-04-09
Hail, III, Joseph J. (Department: 3723)
Abrading
Abrading process
Glass or stone abrading
C451S036000, C451S287000
Reexamination Certificate
active
06368190
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
(Not Applicable)
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
(Not Applicable)
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the field of semiconductor wafer fabrication, and more particularly to the field of electrochemical mechanical planarization (ECMP) of thin films used in semiconductor wafer fabrication.
2. Description of the Related Art
The production of integrated circuits begins with the creation of high quality semiconductor wafers. A semiconductor wafer typically includes a substrate, such as a silicon or gallium arsenide wafer, on which a plurality of transistors have been formed. Transistors are chemically and physically connected into a substrate by patterning regions in the substrate and layers on the substrate. The transistors are interconnected through the use of well known multilevel interconnects to form functional circuits. Typical multilevel interconnects are comprised of stacked thin films, with the interconnect layers consisting of one or more of the following: titanium (Ti), titanium nitrite (TiN), tantalum (Ta), aluminum-copper (Al—Cu), aluminum-silicon (Al—Si), copper (Cu), and tungsten (W).
During the wafer fabrication process, the wafers may undergo multiple masking, etching, dielectric deposition, and conductor deposition processes. An extremely flat, or planarized, surface is generally needed to ensure proper accuracy and performance of the photolithographic processes used in printing even smaller line widths. In general, a wafer can be polished to remove high typography, surface defects such as crystal lattice damage when polishing silicon or GaAs substrates, scratches, roughness or embedded particles. The polishing of metal interconnect layers is necessary to ensure that the metal is left only at the via or plug level, and is not overlying the surface so as to cause unwarranted electrical shorts. As the size of integrated circuits continues to decrease and the density of microstructures on an integrated circuit continues to increase, the need for more planar wafer surfaces becomes more important. Therefore, between each processing step, it is usually necessary to polish the surface of a wafer in order to obtain the most planarized surface possible.
CMP is routinely used to planarize the surface of the layers, or thin films, of the wafer during the various stages of device fabrication. CMP has emerged as the planarization method of choice because of its ability to planarize over longer lengths than traditional planarization methods. During a CMP process, polishing planarizes surfaces to very precise tolerances, which is essential for maintaining the precise photolithographic depth of focus required for integrated circuit chip fabrication. In a typical CMP process, the wafer is held by a rotating carrier with the active wafer surface facing a rotating polishing table, called a platen. On top of the platen is a porous polishing surface on which is poured a slurry. The slurry can be in an aqueous solution in which an abrasive such as colloidal silica is suspended. Slurries with different chemical compositions are used to polish metals and other films. During metal polishing, the slurry chemically reacts with the wafer's surface, forming a passive layer on a portion of the wafer's surface, while the mechanical force exerted by the pad and the abrasive particles abrades the wafer's surface, removing the passive layer.
A CMP slurry serves several functions. Most notably, it is the medium in which abrasive particles are dispersed. Additionally, it furnishes the chemical agents which promote the chemical process. To obtain optimum results from CMP processing, there must be a synergistic relationship between the chemical and mechanical processes.
For example, CMP slurries for polishing a metal layer commonly comprise a metal oxidizer and an abrasive agent. The oxidizer reacts with the metal to form a passive metal oxide layer. During the polishing process, the abrasive agent removes the passive oxide layer from elevated portions of the metal layer. Depressed portions of the metal layer surface are not subjected to mechanical abrasion and, therefore, the protected material underlying depressed portions of the passive oxide layer is not polished. This process continues until the elevated portions of the metal layer have been polished away, resulting in planarization.
The ideal polishing process can be described by Preston's equation: R=K
p
*P*V, where R is the removal rate, P is the applied pressure between the wafer and the polishing surface, V is the relative velocity between the wafer and the polishing surface, and K
p
is a function of consumables such as polishing surface roughness, elasticity, and chemistry. The ideal CMP process has constant pressure between the polishing surface and the wafer, constant polishing surface roughness, elasticity, area, and abrasion effects, and constant velocity over the entire wafer surface.
It is known that the planarizing of a metal layer of a semiconductor wafer can be assisted by the use of an electrolytic polishing slurry in a process known as electrochemical mechanical planarization (ECMP). The metal layer of the semiconductor wafer, the slurry, and a suitable cathode are connected to a voltage potential such that metal ions are driven from the metal layer of the semiconductor wafer into the electrolytic solution. The metal ions either plate at the cathode or are washed away with the electrolytic solution. The control of system parameters, including the concentration of electrolyte in the electrolytic slurry and the voltage potential that is applied to the system, will affect the rate at which metal ions are removed from the metal layer. One such system is disclosed by Uzoh et al, U.S. Pat. No. 5,911,619. It is important to control the current density flowing through the metal layer of the semiconductor wafer, as differences in current density will result in uneven removal of metal ions from different portions of the metal layer. Also, such systems position the cathode beneath the polishing the pad. Gas which can form at the cathode can cause gas bubbles to form underneath the pad during the polishing process and result in uneven planarization.
SUMMARY OF THE INVENTION
An electrochemical mechanical planarization apparatus includes a rotatable platen and a polishing pad that is disposed on the platen and has top and bottom surfaces. A wafer carrier is disposed proximate to the platen and is adapted to hold a wafer against the platen. At least one carrier electrode is disposed on the carrier and is adapted to electrically connect an electrically conductive surface of the wafer held by the carrier to an electrolytic circuit. A platen electrode is operatively connected to the platen and is adapted to connect an electrolytic solution disposed on the polishing pad to the electrolytic circuit. The platen electrode has a substantially circular circumference for radially discharging current into the electrolytic solution. The cathode is substantially, and preferably totally, devoid of portions under the bottom surface of the polishing pad.
In one embodiment, the platen electrode is disposed on the platen around the circumference of the polishing pad. In another embodiment, the polishing pad is substantially ring shaped with an interior opening. The platen electrode is disposed on the platen within the interior opening of the polishing pad.
The platen electrode can also be provided in the polishing pad, which is positioned on the platen. The platen electrode can be provided as a circumferential portion of the polishing pad. In another embodiment, the polishing pad is substantially ring-shaped with an interior opening. The platen electrode is disposed in the polishing pad at a position bordering the interior opening.
REFERENCES:
patent: 5575706 (1996-11-01), Tsai et al.
patent: 5597442 (1997-01-01), Chen et al.
patent: 5624300 (1997-04-01), Kishii et al.
patent: 5647792 (1997-07-01), Katsuoka
Easter William G.
Maze, III John A.
Miceli Frank
Agere Systems Guardian Corp.
Hail III Joseph J.
Ojini Anthony
LandOfFree
Electrochemical mechanical planarization apparatus and method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Electrochemical mechanical planarization apparatus and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electrochemical mechanical planarization apparatus and method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2921100