Electro-thermal nested die-attach design

Details Electro-thermal nested die-attach design Electro-thermal nested die-attach design

1998-01-20

2000-07-18

Niebling, John F.

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

438118, 438119, H01L 2144, H01L 2148, H01L 2150

Patent

active

060906413

ABSTRACT:
A design having a semiconductor microchip bonded to a circuit board is described. This design may include: a printed circuit board (58); a semiconductor microchip (56) bonded to the circuit board (58) by means of an adhesive layer placed between the bonding surface of the microchip (56) and the desired bonding site on the circuit board (58); the adhesive layer providing for thermal relief as well as electrical contact between the microchip (56) and circuit board (58), and consisting of two or more concentric regions that adjoin but do not overlap one another; one being a center core region (50) of thermally and electrically conductive material; the other being a perimeter region (54) of thermally conductive and electrically nonconductive material surrounding the center core region (50) such that the perimeter region's (54) inner boundary completely bounds the center core region (50), and such that the perimeter region's (54) outer boundary extends to a lead on the microchip (56). Other devices, systems, and methods are also disclosed.

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patent: 5653019 (1997-08-01), Bernhardt et al.
patent: 5745985 (1998-05-01), Ghosh et al.

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