Electricity: electrical systems and devices – Safety and protection of systems and devices – Transient responsive
Reexamination Certificate
2002-04-17
2004-06-29
Salata, Jonathan (Department: 2837)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Transient responsive
C361S056000
Reexamination Certificate
active
06757148
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to integrated circuit devices, and more particularly relates to a device for protecting an integrated circuit from damage which can be caused by electro-static discharge into an input terminal.
2. Description of the Prior Art
A chronic problem associated with semiconductor integrated circuits is the destruction which can be caused by electrostatic discharge (ESD) into any one of the external connector pins. A common solution to the problem is when electrostatic discharge intrudes in the die, the electrostatic discharge could flow into a ground terminal to protect interior circuit from damage.
One of conventional layouts to create such a shunt path is shown in
FIG. 1. A
pull-up transistor
105
has an input node coupled to the pad
101
of the integrated circuit chip and the other two input nodes coupled to the supply potential V
DD
of the chip. A pull-down transistor
106
has an input node coupled to the pad
101
and the other two input nodes coupled to the ground potential V
SS
of the chip. A resistor
107
has a terminal coupled to the pull-up transistor
105
, the pad
101
, and the pull-down transistor
106
, and the other terminal coupled to the input stage of the integrated circuit chip. A second-stage transistor
103
has an input node coupled to the input stage and the other two input nodes coupled to the ground potential V
SS
of the chip.
Another of conventional layouts to create such a shunt path, especially for high voltage devices, is shown in
FIG. 2. A
field oxide device (FOD)
102
has an input node coupled to the pad
101
of the integrated circuit chip and the other input node coupled to the ground potential V
SS
of the chip. A resistor
104
has a terminal coupled to the pad
101
and the field oxide device
102
, and the other terminal coupled to the input stage of the integrated circuit chip. A second-stage transistor
103
has an input node coupled to the input stage and the other two input nodes coupled to the ground potential V
SS
of the chip. On consideration of electro-static discharge (ESD) protection performance, a FOD type ESD device needs smaller layout area than a MOS type ESD device does.
However, there are several disadvantages for the FOD type protection device. First, the FOD usually has a long channel length for avoiding the leakage current in a normal operation mode, which results in a low turn-on speed and further ESD failure in an ESD machine model. Second, when the protection mechanism of the POD is triggered by an n+/p junction breakdown, enormous heat occurs at the cylindrical junction of the POD and thus reduces the ESD level. Third, the POD implemented by a LOCOS process has better performance than one by a STI (Shallow Trench Isolation) process. Unfortunately, STI is extensively used in sub-micron (less than 0.25 um) or deep sub-micron technology, so that the performance of the POD is poor. In addition, when the FOD is used in the ESD protection device, there is no corresponding pull-up ESD protection device in the MOS type protection device. Thus, ESD tests of ND mode (“negative” electrostatic is discharged from an input terminal to V
DD
) and PD mode (“positive” electrostatic is discharged from the input terminal to V
DD
) wouldn't be efficiently executed with the POD type protection device.
SUMMARY OF THE INVENTION
It is a principal object of the present invention to provide a protection device for integrated circuits. The performance of ESD tests of ND and PD modes of a POD type ESD protection device are improved with a component building up an effective and short electrical path.
It is another object of the present invention to provide an ESD protection device with less layout area in cooperated with ESD tests of strengthened ND and PD modes.
It is further object of the present invention to provide a FOD type protection device with improved effective junction area by adding structures of polysilicon square on the FOD device. The structures of polysilicon square further avoid junction overheat and poor turn-on characteristics.
In the present invention, an ESD (Electro-Static Discharge) protection device is for an integrated circuit having an input pad. The ESD protection device comprises a pull-up means, such as a MOS transistor, connected between a supply potential and a ground potential of the integrated circuit for PD and ND ESD modes. A first-level protection means, such as a field oxide device, has an input terminal coupled to the input pad and an output terminal coupled to the ground potential. The output terminal of the first-level protection is shared with the pull-up means for saving layout area. The first-level protection means provides passing an ESD current from the input pad into the pull-up means with the ground potential is floating.
REFERENCES:
patent: 5612790 (1997-03-01), Sakamoto et al.
patent: 6222710 (2001-04-01), Yamaguchi
patent: 6608744 (2003-08-01), Kato
patent: 6621673 (2003-09-01), Lin et al.
patent: 2002/0181177 (2002-12-01), Ker et al.
patent: 2003/0072116 (2003-04-01), Maloney et al.
patent: 2003/0076639 (2003-04-01), Chen
patent: 2003/0147188 (2003-08-01), Hisaka
Rosenberg , Klein & Lee
Salata Jonathan
Winbond Electronics Corporation
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