Electricity: electrical systems and devices – Safety and protection of systems and devices – Impedance insertion
Patent
1989-05-12
1991-09-24
Deboer, Todd E.
Electricity: electrical systems and devices
Safety and protection of systems and devices
Impedance insertion
361 56, 361 91, 361111, 357 2313, H02H 904
Patent
active
050518607
ABSTRACT:
An electrostatic discharge protection circuit employing an extended resistive structure having bimodal resistance characteristics in series with an input/output buffer circuit and an input/output electrical contact pad on an integrated circuit. The extended resistive structure is integrally formed with the device or devices in the buffer circuit most susceptible to damage due to ESD breakdown effects. In a first resistance mode during normal circuit operations, the resistor has a low resistance value and introduces virtually no additional load to the input/output buffer circuitry. In a second mode of operation during ESD discharge, the resistor has a second significantly higher resistance which reduces current values during the ESD event thereby protecting the buffer circuit. Thick oxide snap-back device is also employed to provide a parallel ESD discharge path with low power dissipation.
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N. H. E. Weste et al., "Principles of CMOS VLSI Design", pp. 224-231, Addion-Wesley Publishing Company.
E. Fujishin et al., "Optimized ESD Protection Circuits for High-Speed MOS/VLSI", Proc. Custom Integrated Circuits Conference, May 1984, p. 569.
A. Ochoa, Jr., et al., "Snap-Back: A Stable Regenerative Breakdown Mode of MOS Devices", IEEE Trans. on Nuclear Science, vol. NS-30, No. 6, Dec. 1983, p. 4127.
L. R. Avery, "Using SCR's as Transient Protection Structures in Integrated Circuits", RCA DSRC, Princeton, N.J.
Lee Alan
Lee Kowk Fai V.
Marmet Melvin L.
Ouyang Kenneth W.
Deboer Todd E.
Western Digital Corporation
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