Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2001-12-14
2004-06-22
Nguyen, Chanh (Department: 2675)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S100000
Reexamination Certificate
active
06753839
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to an electro-optical panel having two transistor elements per pixel, and to an electronic device using the electro-optical panel.
2. Description of Related Art
Currently, a conventional liquid-crystal display panel include a component substrate, an opposing substrate, and a liquid crystal held between these substrates. A plurality of data lines and a plurality of scanning lines are formed in an image display area of the component substrate, and a thin-film transistor (TFT) is provided in each of the pixels arranged in a matrix in such a manner as to correspond to the intersections thereof.
Various types of pixel circuit construction have been proposed, and in one such pixel construction, a P-channel TFT and an N-channel TFT are used in combination.
FIG. 26
shows an exemplary circuit diagram having a circuit corresponding to one pixel of a component substrate used in a conventional liquid-crystal device. In this figure, the source electrodes of a P-channel TFT
1
and an N-channel TFT
2
are connected to a data line
6
, whereas the gate electrode of the P-channel TFT
1
is connected to a scanning line
5
a
and the gate electrode of the N-channel TFT
2
is connected to a scanning line
5
b.
Also, the drain electrodes of the P-channel TFT
1
and the N-channel TFT
2
are connected to a pixel electrode
3
, and the drain electrode of the N-channel TFT
2
is connected to a holding capacitor
4
. Here, the pixel electrode
3
, the common electrode formed on the opposing substrate, and the liquid crystal forms a liquid-crystal capacitor.
In such a pixel construction, an image signal supplied to the data line
6
can be written into a liquid-crystal capacitor
7
and the holding capacitor
4
when the P-channel TFT
1
and the N-channel TFT
2
are turned on. Then, when the P-channel TFT
1
and the N-channel TFT
2
are turned off, the voltage written into the liquid-crystal capacitor
7
and the holding capacitor
4
is held. Since the transmittance of the liquid crystal varies according to the applied voltage, it become possible to produce a gray-scale display.
Here, the reason the holding capacitor
4
is provided in addition to the liquid-crystal capacitor
7
is that a decrease in the applied voltage to the liquid crystal due to off-leakage of the P-channel TFT
1
and the N-channel TFT
2
is prevented and crosstalk in the vertical direction is prevented.
In the above-described pixel construction, the writing path of the image signal with respect to the holding capacitor
4
differs between a case in which the image signal passes through the P-channel TFT
1
and a case in which the image signal passes through the N-channel TFT
2
. In other words, as shown in
FIGS. 27 and 28
, when the image signal passes through the P-channel TFT
1
, the image signal is written into the holding capacitor
4
via the pixel electrode
3
, whereas when the image signal passes through the N-channel TFT
2
, the image signal is directly written into the holding capacitor
4
without passing through the pixel electrode
3
.
FIG. 27
shows an exemplary circuit diagram having an equivalent circuit for the case in which an image signal is written into the holding capacitor
4
via the N-channel TFT
2
.
FIG. 28
shows a circuit diagram having an equivalent circuit for the case in which an image signal is written into the holding capacitor
4
via the P-channel TFT
1
. In these figures, reference character Ron denotes an ON resistance of the P-channel TFT
1
and the N-channel TFT
2
. Reference character Rito denotes the equivalent resistance of the pixel electrode
3
. Reference character Ch denotes the capacitance value of the holding capacitor
4
.
As is clear from these figures, the time constant when the image signal passes through the N-channel TFT
2
is “Ron·Ch”, whereas the time constant when the image signal passes through the P-channel TFT
1
is “(Ron+Rito)·Ch”. Here, the equivalent resistance Rito of a pixel electrode
8
is greater than the ON resistance Ron.
Therefore, when the image signal is written from the P-channel TFT
1
, the time constant becomes greater than in the case in which the image signal is written from the N-channel TFT
2
. For this reason, when the difference between the voltage of the holding capacitor
4
and the voltage of the image signal is large, the image signal cannot be sufficiently written when it passes through the P-channel TFT
1
, presenting the problem that a large contrast ratio cannot be obtained.
In particular, when a high-resolution image is to be displayed, the number of the scanning lines
5
a
and
5
b
, and the data lines
6
is increased. The greater the number of the scanning lines
5
a
and
5
b
and the data lines
6
is increased, the shorter the selection period of the scanning lines
5
a
and
5
b
and the data lines
6
becomes. As a result, insufficient writing due to the difference in the time constants becomes a serious problem.
SUMMARY OF THE INVENTION
The present invention has been made in view of the above-described circumstances. An object of the present invention is to provide an electro-optical panel which is capable of effectively exhibiting the features of the construction in which two transistor elements are used per pixel, and an electronic device using the electro-optical panel.
To achieve the above-mentioned object, the electro-optical panel of the present invention can include a component substrate, an opposing substrate, and an electro-optical material held between the component substrate and the opposing substrate. The component substrate can further include a plurality of scanning lines which are provided as pairs, a plurality of data lines, pixel electrodes which are arranged in a matrix in such a manner as to correspond to the intersections of the scanning lines and the data lines and which are each arranged between one of the scanning lines and the other of the scanning lines which are provided as a pair, a first transistor element in which the gate electrode is connected to one of the scanning lines which are provided as a pair, the data lines are connected to the source electrode, and the pixel electrode is connected to the drain electrode. The component substrate can further include a second transistor element in which the other one of the scanning lines in the pair is connected to the gate electrode, the data lines are connected to the source electrode, and the pixel electrode is connected to the drain electrode, a capacitance element which is connected to the drain electrode of the second transistor element and wiring which connects the drain electrode of the first transistor element to the drain electrode of the second transistor element.
According to the present invention, since wiring for connecting the drain electrode of the first transistor element to the drain electrode of the second transistor element is provided, the drain electrode of the first transistor element is connected to the drain electrode of the second transistor element through a different path from the pixel electrode. Therefore, since the equivalent resistance between the two drain electrodes is smaller than that in the case where wiring is not provided, the time constant when a signal is written into the holding capacitor via the first transistor element can be decreased.
Here, the resistance of the wiring is preferably smaller than the equivalent resistance of the pixel electrode which connects the drain electrode of the first transistor element to the drain electrode of the second transistor element. Furthermore, from the viewpoint of a lower resistance, it is preferable for the wiring that a high-melting point material, such as aluminum, silver, or chromium, be used. By decreasing the resistance of the wiring in this manner, the time constant when a signal is written into the holding capacitor via the first transistor element can be decreased even more. When the selection period of the scanning lines and the data lines is short, the im
Bell Paul A.
Nguyen Chanh
Oliff & Berridg,e PLC
Seiko Epson Corporation
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