Liquid crystal cells – elements and systems – Particular structure – Having significant detail of cell structure only
Reexamination Certificate
2002-02-08
2003-06-10
Chowdhury, Tarifur R. (Department: 2871)
Liquid crystal cells, elements and systems
Particular structure
Having significant detail of cell structure only
C349S153000, C349S138000
Reexamination Certificate
active
06577371
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to substrates for electro-optical devices such as a reflective liquid crystal panel substrate, and particularly relates to an electro-optical device substrate comprising a pixel region formed on an element region for selecting a pixel.
2. Description of Related Art
The present applicant disclosed configurations of a liquid crystal panel substrate, a liquid crystal panel and a projection display device in Japanese Patent Application No. 8-279388 filed on Oct. 22, 1996, as described below. The projection display device (liquid crystal projector) using a reflective liquid crystal panel as a light valve includes, as shown in
FIG. 17
, a light source
110
arranged along the system optical axis L
0
; a polarized light illumination unit
100
including an integrator lens
120
and a polarized light converter
130
; a polarized light beam splitter
200
for reflecting the S-polarized light beam emitted from the polarized light illumination unit
100
by an S-polarized light reflecting face
201
; a dichroic mirror
412
for separating the blue light component (B) from the light reflected by the S-polarized light reflecting face
201
of the polarized light beam splitter
200
; a reflective liquid crystal light valve
300
B for modulating the separated blue light component (B); a dichroic mirror
413
for separating by reflection the red light component (R) from the light beams after separation of the blue light by a dichroic mirror
412
; a reflective liquid crystal light valve
300
R for modulating the separated red light component (R); a reflective liquid crystal light valve
300
G for modulating the residual green light component (G) passing through the dichroic mirror
413
; a projection optical system
500
including a projection lens for projecting synthesized light onto a screen
600
, in which the light components modulated in the three reflective liquid crystal light valves
300
R,
300
G and
300
B are synthesized by the dichroic mirrors
413
and
412
and the polarized light beam splitter
200
in their reverse paths. Reflective liquid crystal panel
30
shown in
FIG. 18
as a cross-sectional view are used as the reflective liquid crystal light valves
300
R,
300
G and
300
B.
The reflective liquid crystal panel
30
includes a reflective liquid crystal panel substrate
31
fixed with an adhesive on a supporting substrate
32
composed of glass or ceramic; a glass substrate
35
which is provided with a counter electrode (common electrode)
33
composed of a transparent conductive (ITO) film, and which lies at the incident light side, and is opposed with a gap to the reflective liquid crystal panel substrate
31
enclosed by a frame composed of a sealing agent
36
; and a known twisted nematic (TN) liquid crystal or a super homeotropic (SH) liquid crystal
37
in which liquid crystal molecules are vertically aligned in a no-applied voltage state, the liquid crystal being sealed in the space enclosed by the sealing agent
36
between the reflective liquid crystal panel substrate
31
and the glass substrate
35
.
FIG. 19
is a plan view of an enlarged layout of a reflective liquid crystal panel substrate
31
used in the reflective liquid crystal panel
30
. The reflective liquid crystal panel substrate
31
includes a rectangular pixel region (display region)
20
provided with pixel electrodes disposed in matrix
14
shown in
FIG. 18
; gate line driver circuits (Y drivers)
22
R and
22
L lying at the exteriors of the right and left sides of the pixel region
20
for scanning gate lines (scanning electrodes or line electrodes); a precharging/testing circuit
23
lying at the exteriors of the upper side of the pixel electrode
14
for data lines (signal electrodes or column electrodes); an image signal sampling circuit
24
lying at the exterior of the bottom side of the pixel electrodes
14
for supplying image signals to the data lines in response to the image data; a sealing region
27
with a frame shape lying at the exterior of the gate line drivers
22
R and
22
L, the precharging/testing circuit
23
and the image signal sampling circuit
24
, for placing a sealing agent
36
; a plurality of terminal pads
26
arranged along the bottom end and connected to a flexible tape wiring
39
with an anisotropic conductive film (ACF)
38
therebetween; a data line driver circuit (X driver)
21
lying between the terminal pad array
26
and the sealing region
27
for supplying image signals to data lines in response to the image data; and relay terminal pads (so-called silver points)
29
R and
29
L lying beside both ends of the data line driver circuit
21
for energizing the counter electrode
33
on the glass substrate
35
.
The peripheral circuits (the gate line driver circuits
22
R and
22
L, the precharging/testing circuit
23
and the image signal sampling circuit
24
) lying at the interior of the sealing region
27
have a shading film
25
(refer to
FIG. 18
) to shield from the incident light, which is the same as the pixel electrodes
14
of the topmost layer.
FIG. 20
is an enlarged partial plan view of the pixel region
20
of the reflective liquid crystal panel substrate
31
, and
FIG. 21
is a cross-sectional view taken along the line A-A′ of FIG.
20
. In
FIG. 21
, numeral
1
represents a single-crystal silicon P
−
semiconductor substrate (an N
−
semiconductor substrate is also available) having a side of 20 mm. Numeral
2
represents a P-type well region formed on the top surface (main face) in the device-forming region (MOSFET etc.) of the semiconductor substrate
1
, and numeral
3
represents a field oxide film (so-called LOCOS) which is formed for separating devices in the non-element-forming region of the semiconductor substrate
1
. The p-type well region
2
shown in
FIG. 21
is formed as a common well region for the pixel region
20
provided with a matrix of pixels having dimensions of, for example, 768×1024, and it is separated from a P-type well region
2
′ (refer to
FIG. 22
) for fabricating the devices of the peripheral circuits (the gate line driver circuits
22
R and
22
L, the precharging/testing circuit
23
, the image signal sampling circuit
24
and the data line driver
21
).
The field oxide film
3
is provided with two openings in the divided region of each pixel. A gate electrode
4
a
composed of polycrystalline silicon or a metal silicide is formed via a gate insulating film
4
b
in the center of one opening; an N
+
source region
5
a
, and an N
+
drain region
5
b
formed on the P-type well region
2
at the both sides of the gate electrode
4
a
form a N-channel MOSFET (insulated-gate field effect transistor) for pixel selection together with the gate electrode
4
a
. Gate electrodes
4
a
in a plurality of pixels arrayed in a line extend in the scanning line direction (the line direction of the pixels) to form gate lines
4
.
A P-type capacitor electrode region
8
, which is common to the line direction, is formed on the P-type well region
2
in the other opening; a capacitor electrode
9
a
composed of polycrystalline silicon or a metal silicide formed on the P-type capacitor electrode region
8
with an insulating film (dielectric film)
9
b
therebetween forms a retention capacitor C for retaining a signal selected by the MOSFET for pixel selection together with the P-type capacitor electrode region
8
.
A first interlayer insulation film
6
is formed on the gate electrode
4
a
and the capacitor electrode
9
a
, and a first metal layer composed mainly of aluminum is formed on the insulating film
6
.
The first metal layer includes a data line
7
(refer to
FIG. 20
) extending in the column direction, a source electrode wiring
7
a
, which protrudes from the data line
7
in a comb shape and is brought into conductive contact with a source region
5
a
through a contact hole
6
a
, and a relay wiring
10
which is brought into conductive contact with the drain region
5
b
through a contac
Chowdhury Tarifur R.
Oliff & Berridge PLC.
Seiko Epson Corporation
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