Optical: systems and elements – Optical modulator – Light wave temporal modulation
Reexamination Certificate
2001-04-11
2003-07-15
Schwartz, Jordan M. (Department: 2873)
Optical: systems and elements
Optical modulator
Light wave temporal modulation
C359S254000, C359S259000
Reexamination Certificate
active
06594064
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to an electro-optical device composed of a semiconductor layer on a substrate, a manufacturing method for manufacturing the electro-optical device, and electronic equipment. In particular, the present invention relates to an electro-optical device having a channel region of the semiconductor layer connected to a light-shielding layer, a manufacturing method for manufacturing the electro-optical device, and electronic equipment.
2. Description of Related Art
The SOI (Silicon On Insulator) technology, which forms a semiconductor of a monocrystal silicon layer on an insulator substrate and then produces a semiconductor element such as a transistor on the semiconductor layer, is advantageous in the implementation of high-speed and power-saving design, and of the high degree of integration into elements. For example, the SOI technology finds applications in a switching element in a TFT array in an electro-optical device such as a liquid-crystal display device.
In typical bulk semiconductor parts, the channel region of a transistor is kept to a predetermined potential through a substrate thereof, and the element is thus free from the electrical characteristic degradation attributed to parasitic bipolar effect resulting from a change in the potential of the channel.
SUMMARY OF THE INVENTION
Since a transistor forming a switching element of a TFT array is completely isolated by an oxide insulator in an electro-optical device such as a liquid-crystal display device, the channel region of the transistor cannot be kept to a predetermined potential unlike a bulk semiconductor transistor. For this reason, the channel region remains electrically floating. In particular, when the transistor has a structure of a monocrystal silicon layer, the mobility of carriers traveling within the channel region is high. Carriers accelerated by the electric field in the vicinity of the drain region of the transistor impact the crystal lattice, leading to a phenomenon called impact ionization. As a result, holes, generated in an N-channel TFT, are accumulated in the bottom portion of the channel. When charges are accumulated in the channel in this way, the NPN structure of the TFT (in case of the N-channel TFT) apparently functions as a bipolar device. An abnormal current lowers the element source-drain withstand voltage, leading to electrical characteristic degradation. A group of phenomena attributed to the electrically floating channel is called a substrate floating effect.
It is an object of the present invention to provide an electro-optical device which stabilizes and improves electrical characteristics of a transistor having a monocrystal silicon layer covered with an insulator layer, by preventing the transistor source-drain withstand voltage from being lowered by the substrate floating effect.
An electro-optical device of one exemplary embodiment of the present invention includes, on a support substrate, a plurality of scanning lines, a plurality of data lines which intersects the plurality of scanning lines, a transistor connected to each of the scanning lines and each of the data lines, a pixel electrode connected to each transistor, an insulator layer, formed beneath a semiconductor layer of the transistor serving as a channel of the transistor, and an electrically conductive light-shielding layer formed between the insulator layer and the support substrate, wherein an extension portion of the semiconductor layer is electrically connected to the light-shielding layer.
Since the channel region of the transistor is connected to the electrically conductive light-shielding layer formed beneath the insulator layer under the semiconductor layer of the transistor in the present invention, the channel region is kept to the potential of the light-shielding layer. No abnormal current flows through the transistor, and the electrical characteristics of the transistor are thus stabilized.
In accordance with another exemplary embodiment of the present invention, the extension portion is preferably connected to the light-shielding layer through an interconnect line that runs through a first contact hole formed in the extension portion and a second contact hole formed in the light-shielding layer. With this arrangement, an existing wiring layer is used as the interconnect line for connecting the extension portion to the light-shielding layer.
This arrangement eliminates the need for arranging a new wiring layer, thereby reducing manufacturing steps.
In accordance with another exemplary embodiment of the present invention, the extension portion is preferably connected to the light-shielding layer through an interconnect line that runs through a first contact hole formed in the extension portion and a second contact hole that penetrates the extension portion in a region including the internal portion of the first contact hole and is formed in the light-shielding layer. This arrangement allows the interconnect line to occupy the smallest possible area, thereby controlling a reduction in the aperture ratio of a light-transmissive region which is important in a transmissive-type liquid-crystal display device.
In accordance with another exemplary embodiment of the present invention, the interconnect line is preferably fabricated of the same layer as the one that forms the data line or the scanning line. Since this arrangement allows the interconnect line to be manufactured together with the data line or the scanning line, the electro-optical device can be produced using a related manufacturing process.
In accordance with another exemplary embodiment of the present invention, the electro-optical device preferably includes a storage capacitor connected to the pixel electrode and formed of the semiconductor layer, a capacitive line fabricated of the same layer as the one that forms the scanning line and running in parallel with the scanning line, and an insulator layer interposed between the semiconductor layer and the capacitive line, wherein either the scanning line or the capacitive line includes a bypass path bypassing the interconnect line. When the storage capacitor is incorporated, this arrangement allows the channel region of the transistor to be connected to the electrically conductive light-shielding layer while efficiently making use of a limited space.
In accordance with another exemplary embodiment of the present invention, the light-shielding layers of the transistors are preferably electrically connected to each other in the direction of the scanning line or in the direction of the data line, or in both the directions of the scanning line and the data line, and are preferably supplied with a predetermined potential. This arrangement controls the potential of the light-shielding layer, thereby preventing variations in the threshold voltage of the transistor formed over the light-shielding layer. The electrical characteristics of the transistor are thus stabilized.
In the above arrangement, preferably, the predetermined potential provided to the light-shielding layer is not higher than the lowest potential applied to the source or the drain of the transistor when the transistor arranged over the light-shielding layer is an N-channel transistor. Preferably, the predetermined potential provided to the light-shielding layer is not lower than the highest potential applied to the source or the drain of the transistor when the transistor arranged over the light-shielding layer is a P-channel transistor. Since electrons or holes generated in the channel with the transistor being driven flow to the light-shielding layer through the extension portion, the potential of the channel region is stabilized. This arrangement controls the substrate floating effect of the transistor, thereby preventing a drop in the withstand voltage of the transistor.
In accordance with another exemplary embodiment of the present invention, the thickness of the semiconductor layer preferably ranges from 100 to 180 nm. The semiconductor layer thicker than 100 nm
Oliff & Berridg,e PLC
Schwartz Jordan M.
Seiko Epson Corporation
Thompson Tim
LandOfFree
Electro-optical device, manufacturing method for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Electro-optical device, manufacturing method for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electro-optical device, manufacturing method for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3107595