Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2006-09-05
2010-10-05
Lao, Lun-Yi (Department: 2629)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S087000, C345S098000, C345S103000, C345S204000, C349S048000, C365S190000, C365S230030
Reexamination Certificate
active
07808470
ABSTRACT:
An electro-optical device includes an X address decoder that selects one of plural X selection lines, a Y address decoder that selects one of plural Y selection lines, and plural pixel blocks. Each pixel block is provided with respect to an intersection of a corresponding X selection line and a corresponding Y selection lines. Each pixel block includes a pixel circuit and the pixel circuits corresponding to a column share a bit line and a complementary bit line. Each pixel circuit includes a memory circuit, a selection circuit, and a pixel electrode. The memory circuit includes plural transistors that become conductive between the bit line, the complementary bit line, and terminals of the memory circuit at the time of concurrent selection of an X selection line and a Y selection line corresponding to the pixel block to which the plural transistors belong.
REFERENCES:
patent: 5945972 (1999-08-01), Okumura et al.
patent: 6127998 (2000-10-01), Ichikawa et al.
patent: 6873320 (2005-03-01), Nakamura
patent: 6965365 (2005-11-01), Nakamura
patent: 7057596 (2006-06-01), Miyazawa
patent: 7592990 (2009-09-01), Miyazawa
patent: 2002/0024485 (2002-02-01), Koyama
patent: 2002/0030648 (2002-03-01), Yamamoto et al.
patent: 2002/0036627 (2002-03-01), Yokoyama
patent: 2002/0047822 (2002-04-01), Senda et al.
patent: 2005/0122457 (2005-06-01), Song
patent: A 08-286170 (1996-11-01), None
patent: A-2001-159883 (2001-06-01), None
patent: A-2002-175040 (2002-06-01), None
patent: A 2002-311902 (2002-10-01), None
patent: A 2002-311903 (2002-10-01), None
patent: A-2003 -302946 (2003-10-01), None
patent: A 2005-189274 (2005-07-01), None
Ozawa Yutaka
Yamazaki Suguru
Epson Imaging Device Corporation
Lao Lun-Yi
Oliff & Berridg,e PLC
Shah Priyank
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