Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1999-10-18
2002-04-30
Hjerpe, Richard (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S098000, C345S559000
Reexamination Certificate
active
06380920
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention generally relates to a drive circuit for an electro-optical device, and more particularly, to a liquid crystal drive circuit having a D/A converter (namely, a digital-to-analog conversion circuit), and to an electro-optical device using this drive circuit, and to electronic equipment using this electro-optical device for displaying an image.
2. Description of Related Art
As shown in
FIG. 10
, a conventional drive circuit for an electro-optical device comprises latching means
91
consisting of a first group of latch circuits XLT
1
-
1
to XLT
3
-
1
, each of which sequentially latches and holds digital image data (hereunder referred to simply as image data) supplied from an external control device to terminals D
0
, D
1
and D
2
, and a second group of latch circuits XLT
1
-
2
to XLT
3
-
2
, to which image data of one line is latched by the first group of latch circuits. This drive circuit further comprises a shift register
92
for generating clock signals, which provide timing in serially latching image data present on data lines L
0
, L
1
and L
2
, according to clocks CLK and {overscore (CLK)} supplied from an external circuit. This drive circuit furthermore comprises a D/A converter
93
adapted to perform the D/A conversion of data (consisting of 3 bits in the case shown in this figure) of each of pixels respectively represented by the image data latched by the second group of latch circuits XLT
1
-
2
to XLT
3
-
2
for supplying predetermined voltages to each signal line in the pixel region.
In the aforementioned drive circuit, image data are input from an external circuit to the data lines L
0
, L
1
and L
2
, respectively. However, the parasitic capacitance of the data lines L
0
, L
1
and L
2
has an extremely large value (which may be 100 pF or more), in comparison with that of wirings of a semiconductor integrated circuit, because of the facts that the length of the aforementioned data lines L
0
, L
1
and L
2
of an electro-optical device reaches several tens of cm and that the electro-optical device has many signal lines intersecting the data lines L
0
, L
1
and L
2
. Thus, the rate of transmission of image data at a point on each of the data lines L
0
, L
1
and L
2
decreases with a reduction in the distance between the point and a tip end thereon, namely, with the distance from a corresponding data input terminal to the point. This results in a decrease in the timing margin of the clock signal providing the first group of latch circuits XLT
1
-
1
through XLT
3
-
1
with data latch timing with which data output from the shift register
92
is latched by the first group of latch circuits XLT
1
-
1
to XLT
3
-
1
. Consequently, it becomes difficult to input image data thereto at a high speed.
Further, the output impedance of an IC for outputting image data should be reduced so as to achieve the high-speed input Of image data. However, the large parasitic capacitance of the data lines L
0
, L
1
and L
2
makes it extremely difficult to realize the high-speed input of image data. For instance, in the case of a liquid crystal panel having a resolution of 640×480 dots and conforming to the VGA (Video Graphic Array) standard, the frequency of an image data input signal is 20 MHz or so. Moreover, in the case of a liquid crystal panel conforming to the SVGA (Super Video Graphics Array) standard, the frequency of an image data input signal reaches 100 MHz. Therefore, it is difficult to realize the high-speed input of image data. Especially, in the case of an electro-optical device using a polysilicon TFT as an element of a drive circuit, at least 3.3 V, preferably, 5 V or more is needed as the amplitude of a signal representing the aforementioned image data. The driving ability of the IC outputting image data should be enhanced so as to input image data to the data lines having large parasitic capacitance at a high speed by using a signal of a large amplitude.
SUMMARY OF THE INVENTION
The present invention is proposed to solve the aforementioned problems of the conventional drive circuit. Accordingly, the present invention provides a drive circuit for an electro-optical device, to which image data can be input at a high speed from an external circuit.
The present invention also provides a drive circuit for an electro-optical device, which is enabled to lower the driving ability of the IC inputting image data and reduce the power consumption thereof.
The present invention also provides a drive circuit for an electro-optical device, which decreases the wiring pitch of signal lines in a pixel area.
The present invention provides a drive circuit for an electro-optical device having a function of performing lateral inversion of an image, which can perform lateral inversion of an image without having what is called a reverse reading circuit for reading image data of one line in a reverse direction from a memory in which image data is stored.
According to an aspect of the present invention, there is provided a drive circuit for an electro-optical device, which is configured so that the shift register is used for latching image data, instead of generating clock signals providing data latching timing to the latch circuit for latching image data input from an external circuit, differently from the conventional drive circuit.
This results in a decrease in the length of each of the data lines between the corresponding image data input terminal and the shift register for latching image data. Thus, in the case of the drive circuit of the present invention, there is no necessity for considering the timing margin of the clock signal providing each of the latch circuits with the latching timing, differently from the conventional drive circuit. Consequently, there is provided a drive circuit for an electro-optical device, which enables the high-speed input of image data to an electro-optical device from an external circuit at a high speed and lowers the driving ability of the IC for inputting image data and reduces the power consumption thereof.
Moreover, according to the present invention, a liquid crystal drive circuit having a D/A converter is configured so that a pair of shift registers for latching image data is provided corresponding to each of bits of the image data, that the image data is latched from an external circuit to one of the shift registers of such a pair, image data of one line latched into the other shift register is simultaneously transferred to the D/A converter, and that a transferring switch for enabling this transfer of such image data is placed between the shift register provided corresponding to each of the bits.
Thus, there is provided a drive circuit for an electro-optical device, which sets the wiring pitch of signal lines in a pixel area at a smaller value, as compared with the case of placing all of the transferring switches at the D/A-converter side.
Furthermore, a delaying shift register is provided in addition to the pair of shift registers corresponding to each of the bits. Moreover, an on-off switch for enabling and/or disabling the transfer of image data is provided between this delaying shift register and an image data input terminal. An on-off switch for enabling and/or disabling the transfer of image data and a changing switch for permitting the transfer of image data to one of the shift registers of this pair are provided between the delaying shift register and another pair of shift registers.
Thus, the switches are controlled to thereby cause the delaying register to operate. Consequently, the lateral inversion of an image can be enabled only by a drive circuit of the present invention without providing what is called a reverse reading circuit, which is used for reading image data of one line from a memory storing the image data in a reverse direction, in an electro-optical device having the function of performing the lateral inversion of an image.
REFERENCES:
patent: 5170158 (1992-12-01), Shinya
patent: 6046719 (2000-04-01), Dengwau
patent: 6049321 (2000-12-01),
Hjerpe Richard
Nguyen Frances
Seiko Epson Corporation
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