Liquid crystal cells – elements and systems – Particular excitation of liquid crystal – Electrical excitation of liquid crystal
Reexamination Certificate
1998-05-29
2004-02-17
Chowdhury, Tarifur R. (Department: 2871)
Liquid crystal cells, elements and systems
Particular excitation of liquid crystal
Electrical excitation of liquid crystal
C349S043000, C349S122000, C257S059000
Reexamination Certificate
active
06693681
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an electro-optical device such as a liquid crystal display device, and particularly to a display device having an active matrix circuit.
2. Description of Prior Art
Recently, an active matrix circuit for driving a liquid crystal display has been actively studied and put into practical use. As an active element has been proposed one having a construction that a conductive-type thin film transistor (TFT) is used for a picture element. Such an active matrix circuit has capacitors each comprising a picture-element electrode, a counter electrode and liquid crystal interposed between these electrodes, and charges to be supplied to and discharged from the capacitor are controlled by a TFT. In order to perform a stable image display, a voltage across both electrodes of each capacitor is required to be kept constant, however, it has been difficult to satisfy this requirement for some reasons.
The most significant reason is that charges leak from the capacitor even when the TFT is in an off-state. There is another leakage of charges inside of the capacitor, however, the former leakage of the charges from the TFT is larger than the latter leakage by about one order. When this leakage occurs intensively, there occurs a phenomenon, so-called flicker that light and darkness of an image is varied at the same frequency as a frame frequency. As another reason, a gate signal is capacitively coupled to a picture-element potential due to parasitic capacitance between a gate electrode of the TFT and the picture-element electrode to induce variation of a voltage (&Dgr;V).
In order to solve these problems, an auxiliary (or additive) capacitance has been disposed in parallel to the picture-element capacitance. Provision of such an auxiliary capacitance causes a time constant of discharging of charges from the picture-element capacitance to be increased. In addition, representing a gate pulse (signal voltage) by V
G
, the picture-element capacitance by C
LC
, the auxiliary capacitance by C, and the parasitic capacitance between the gate electrode and the picture-element electrode by C′, &Dgr;V is represented as follows;
&Dgr;
V=C′V
G
/(
C
LC
+C′+C
)
and &Dgr;V can be reduced if C is larger than C′ and C
LC
.
Conventionally, a circuit construction as shown in FIG.
2
(A) or
2
(B) has been adopted for the auxiliary capacitance. These circuit arrangements are shown by circuit diagrams of FIGS.
2
(C) and
2
(D), respectively. In the circuit arrangement as shown in FIG.
2
(B), a ground line, for example X
n
, is formed in parallel to a gate line X
n
(or data line Y
m
), and a picture-element electrode is formed so as to be overlapped with the ground line, thereby forming a capacitance C. In FIG.
2
(B), the auxiliary capacitance C is represented by an oblique-line portion, and C
LC
represents a picture-element electrode. However, in this circuit arrangement (method), a wiring is required to be newly formed, and thus there is a disadvantage that the aperture ratio is reduced and a screen is darkened.
On the other hand, in the circuit arrangement as shown in FIG.
2
(A), a picture-element electrode which is connected to the gate line X
n
is partially overlapped with a next gate line X
n+1
to form an auxiliary capacitance C (as indicated by an oblique-line portion) at the overlap portion. In this case, no wiring is required to be newly formed, and thus the aperture ratio is not reduced. However, it has been known that a gate pulse is affected by capacitance which is added to the gate line.
At any rate, in these methods (circuit arrangements), substantially no solution have been made particularly to &Dgr;V. These methods provide some degree of effect in a point that the time constant of the discharging of the picture element is lengthened, however, no solution has been made to the point that &Dgr;V occurs asymmetrically. FIG.
3
(C) shows a driving operation of a conventional TFT active matrix circuit. In this case, the potential of a counter electrode of a picture-element electrode is set to “0” V, and the potential of the gate line at non-selection time is also set to “0” V. However, as usually adopted, the potential of the counter electrode may be added with a proper offset potential while the potential of the data line is also added with the same offset potential. Actually, the same result as shown in
FIG. 3
is obtained. Particularly when the potential of the gate line and the potential of the counter electrode are set to zero as shown in
FIG. 3
, the signal of the data line is required not to exceed a threshold voltage of the TFT, and no stable matrix driving can be performed unless this condition is satisfied.
As is apparent from
FIG. 3
, &Dgr;V is shifted with respect to the data signal in such a direction that the potential thereof is decreased. For example, even when an auxiliary capacitance is added to reduce &Dgr;V, the response is still asymmetrical. In this point, the provision of the auxiliary capacitance is a negative countermeasure.
SUMMARY OF THE INVENTION
An object of this invention is to provide a display device and a display method for positively reducing &Dgr;V with a technical idea different from the conventional technical idea, and more particularly to provide an effective arrangement of display picture elements and a circuit arrangement for a display device and the display method.
&Dgr;V is originally caused by application of a pulse to only the gate electrode. If, in addition to a first TFT, the same type of second TFT having the same amount of parasitic capacitance as the first TFT is added in a picture element and a pulse having a different polarity from and the same height as a gate pulse is applied to the second TFT simultaneously with the application of the gate pulse, the contribution of the gate pulse to a picture-element electrode could be offset (counteracted). The inventor of this application has found this technical idea, and further developed the theory of this technical idea. As a result, he has finally found that the same effect can be obtained if any circuit having an equivalently same capacitance may be provided in place of the second TFT which is additively provided.
That is, representing a parasitic capacitance between a gate electrode and a picture-element electrode by C
1
and a parasitic capacitance between a second wiring different from the gate electrode and the picture-element electrode by C
2
, and representing the height of a pulse of the gate electrode by V
1
, and the pulse height of the second wiring by V
2
, &Dgr;V is represented as follows:
&Dgr;
V
=−(
C
1
V
1
+C
2
V
2
)/(
C
1
+C
2
)
If V
2
=0, the data signal would be lowered by &Dgr;V like the prior art. However, if V
2
=−C
1
V
1
/C
2
, &Dgr;V would be equal to zero. For example, for C
1
=C
2
, &Dgr;V is mutually counteracted (offset) and equal to zero by setting V
2
to be equal to V
1
. As described above, in comparison with the conventional method of relatively reducing &Dgr;V by providing the auxiliary capacitance, the method of this invention is a more positive method in the meaning that a voltage increase (variation) capable of counteracting &Dgr;V is generated and &Dgr;V is offset by this voltage increase (variation).
According to further consideration of the inventor, the following matter has been also found. If, irrespective of the complete synchronization between the gate pulse and the pulse of the second wiring, the device is so designed that the pulse of the second wiring is intermitted (dropped or cut) after the gate pulse is intermitted (dropped or cut), the same effect as obtained when the gate pulse and the second-wiring pulse are completely synchronized with each other would be obtained although the potential of the picture-element electrode is temporally varied. The pulse starting time for the gate pulse may be earlier or later than that of the second-wiring pulse because &Dgr;V occurs at the off-time
Chowdhury Tarifur R.
Duong Tai
Robinson Eric J.
Robinson Intellectual Property Law Office P.C.
Semiconductor Energy Laboratory Co,. Ltd.
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