Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2008-07-01
2008-07-01
Shalwala, Bipin (Department: 2629)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S092000
Reexamination Certificate
active
10909560
ABSTRACT:
Aspects of the invention can provide an electro-optical device having n image signal lines to which n serial to parallel converted image signals are supplied. A driving circuit has a sampling circuit that can include a plurality of thin film transistors. Each of the thin film transistors can have (i) a drain connected to a drain wiring line arranged from a data line in a direction in which the data line extends, (ii) a source connected to a source wiring line arranged from the image signal line in a direction in which the data line extends, and (iii) a gate arranged to be sandwiched between the drain wiring line and the source wiring line in a direction in which the data line extends, and the plurality of thin film transistors can be arranged to correspond to the plurality of data lines. Two adjacent thin film transistors with the boundary between thin film transistor groups interposed therebetween among the plurality of thin film transistors can be arranged such that the arrangements of the source and drain wiring lines with a gate interposed therebetween are opposite to each other. By doing so, it is possible to reduce image faults caused by parasitic capacitance located between the thin film transistors in the sampling circuit.
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Mochizuki Hiroaki
Uchida Masahide
Yamasaki Yasuji
Chowdhury Afroza Y
Shalwala Bipin
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