Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2002-03-29
2004-12-21
Nguyen, Vinh P. (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S754120, C324S754120
Reexamination Certificate
active
06833716
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor devices and their fabrication, and more particularly, to techniques for analyzing circuitry within an integrated circuit.
BACKGROUND OF THE INVENTION
The semiconductor industry has recently experienced technological advances that have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors operating at speeds of hundreds of millions of instructions per second to be packaged in relatively small, air-cooled semiconductor device packages.
As the manufacturing processes for semiconductor devices and integrated circuits increase in difficulty, methods for testing and debugging these devices become increasingly important. Not only is it important to ensure that individual chips are functional, it is also important to ensure that batches of chips perform consistently. In addition, the ability to detect a defective manufacturing process early is helpful for reducing the number of defective devices manufactured.
One analysis method involves electro-optic probing of traditional CMOS circuits using, for example, an electro-optic probe commercially available from Schlumberger, ATE Division. Electro-optic probing of voltage waveforms in typical CMOS circuits is possible because a response from an active region in the circuit is generally readily detectable through silicon. For example, source/drain (S/D) regions in CMOS circuits make p-n junctions with well regions. A depletion region exists at the junctions and has a strong electric field responsible for changes in refractive index and in the light absorption coefficient of silicon at the junction. When examined through the bulk silicon, the relatively uncomplicated structure of the CMOS circuits in the junction regions and the strong electric field exhibited by the depletion region both support electro-optic probing of traditional CMOS circuits, whereby a response from the circuits can be detected.
For CMOS circuits using silicon on insulator (SOI) structure, the transistor is fully (both laterally and vertically) isolated and the S/D diffusions extend down to the insulator layer in the SOI structure. Hence, the p-n junctions that exist between the S/D regions and the well in traditional CMOS circuits are absent in SOI circuits. This transistor structure also decreases the drain capacitance substantially, resulting in a faster switching transistor. The absence of the above-mentioned p-n junctions presents challenges to the electro-optic probing of CMOS circuit dies having SOI structure.
In CMOS and other circuits employing SOI structures, interfaces between the different materials in the SOI structures make it difficult to obtain an optical response, for example, due to changes in refractive index that occur at each interface. These changes in refractive index result in undesired reflected light. This undesired reflected light constitutes the background portion of the total (signal+background) reflected light captured by a probe. The background light interferes with the signal, or that portion of the reflected light that is useful, for example, for analyzing circuit functions. Additionally, light reflecting off the interfaces does not impede upon the intended circuitry of interest (e.g., target circuitry). This diminishes the intensity of the light reflected back to the probe from the circuitry of interest, again presenting challenges to circuit analysis.
SUMMARY OF THE INVENTION
The present invention is directed to approaches for overcoming the above and other challenges to analyzing a semiconductor device having SOI structure, as exemplified in a number of implementations and applications, some example aspects of which are summarized below.
According to an example embodiment of the present invention, an electro-optic probe is directed at a selected portion of an integrated circuit die having silicon on insulator (SOI) structure. The integrated circuit die is stimulated, and the electro-optic probe is dynamically focused at the selected circuit portion, using select variations in focus parameters (e.g., small adjustments in correction ring settings of a microscope portion of the electro-optic probe). A response of the selected circuit portion to the focused electro-optic probe is detected and used for analyzing the integrated circuit die. In one implementation, the response includes a voltage waveform at selected focus settings, and the waveform is used to analyze a circuit characteristic (e.g., a voltage state) of the integrated circuit device.
According to another example embodiment of the present invention, an electro-optic crystal is positioned at a selected portion of the integrated circuit die, and a probe is directed thereto. The integrated circuit die is stimulated and a response of the crystal to the stimulation is detected in this manner, probing of an integrated circuit die having SOI structure is achieved, and electrical characteristics of the die are readily detected via the response of the crystal.
According to another example embodiment of the present invention, an integrated circuit die having SOI structure layer is analyzed with an electro-optic probe via an exposed portion of the insulator having an anti-reflective coating thereon. The anti-reflective coating inhibits unwanted reflections from the die during probing. The integrated circuit die is stimulated, and the electro-optic probe is focused to a selected portion of the chip circuitry. A response from the probe is detected and the die is analyzed therefrom.
In another example embodiment, a refractive index matching fluid is placed onto an exposed portion of the insulator of a SOI structure. An anti-reflective coating is then introduced above the exposed insulator layer by placing an optically transparent substrate that incorporates an anti-reflective coating, such as on a top or bottom side of the substrate. The chip is then stimulated. The electro-optic probe is focused to the SOI structure through the optically transparent substrate and the index matching fluid, thereby generating an optical response suitable for analysis of the die. Reflections from the beam are inhibited by the antireflective coating, improving the ability to detect the optical response. In a more particular implementation, an anti-reflective coating is placed on the exposed portion of the insulator prior to placing the index matching fluid.
In another example embodiment, a system is arranged for analyzing an IC die having SOI structure with a probe. The system includes a stimulation device adapted to stimulate the integrated circuit die and effect a response of the die, and in one implementation, to effect a response of an electro-optic crystal located at the die. A detection arrangement is configured and arranged to detect a response of the die, directly and/or indirectly (e.g., using the electro-optic crystal).
The above summary is not intended to describe each illustrated embodiment or every implementation. The figures and detailed description that follow more particularly exemplify these embodiments.
REFERENCES:
patent: 5638005 (1997-06-01), Rajan et al.
patent: 6326798 (2001-12-01), Kuribara
patent: 6653849 (2003-11-01), Bruce et al.
Bruce Michael R.
Dabney Greg
Goruganthu Rama R.
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