Electro-luminescence panel

Details Electro-luminescence panel Electro-luminescence panel

2001-12-21

2004-02-17

Philogene, Haissa (Department: 2821)

Electric lamp and discharge devices: systems

Plural power supplies

Plural cathode and/or anode load device

C315S169200, C315S169300, C345S204000, C345S214000

Reexamination Certificate

active

06693383

ABSTRACT:

This application claims the benefit of Korean Patent Application No. 2000-81417, filed on Dec. 23, 2000, the entirety of which is hereby incorporated by reference for all purposes as if fully set forth herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an electro-luminescence display (ELD), and more particularly to an electro-luminescence panel that is capable of improving brightness.
2. Description of the Related Art
Recently, various flat panel display devices have been developed with reduced weight and bulk that are capable of eliminating the disadvantages associated with a cathode ray tube (CRT). Such flat panel display devices include liquid crystal displays (LCD), field emission displays (FED), plasma display panels (PDP) and electro-luminescence (EL) panels.
Studies have been made increasing the display quality of the flat panel display device and for providing the flat panel display with a large-scale screen. The EL panel in such display devices is a self-emission device. The EL panel excites a fluorescent material using carriers such as electrons and holes, to display a video image. The EL panel has advantages in that a low direct current driving voltage is possible and the response speed is fast.
Referring to
FIG. 1
, the conventional EL panel includes gate line pairs GL and /GL and data lines DL arranged on a glass substrate
10
in such a manner to cross each other, and pixel elements PE arranged at each crossing of the gate line pairs GL and /GL and the data lines DL. Each pixel element PE is driven when gate signals at the gate line pairs GL and /GL are enabled, to thereby generate light corresponding to the magnitude of pixel signals at the data lines DL.
In order to drive such pixel elements PE, a gate driver
12
is connected to the gate line pairs GL and /GL while a data driver
14
is connected to the data lines DL. The gate driver
12
drives the gate line pairs GL and /GL sequentially. The data driver
14
applies pixel signals to the pixels PE via the data lines DL.
Each of the pixel elements PE driven with the gate driver
12
and the data driver
14
in this manner includes an EL cell, that is, an organic light emitting diode OLED connected to a ground voltage line GND, and a cell driving circuit
16
for driving the EL cell OLED. The EL cell OLED emits light corresponding to an amount of current applied from the cell driving circuit
16
.
Referring to
FIG. 2
, the cell driving circuit
16
includes a first PMOS thin film transistor (TFT) MP
1
connected between first and second nodes N
1
and N
2
, and the EL cell OLED, a second PMOS TFT MP
2
connected between the second node N
2
and the EL cell OLED, and a capacitor C
1
connected between the first and second nodes N
1
and N
2
.
The capacitor C
1
charges a voltage of a pixel signal when the pixel signal is received from the data line DL and applies the charged pixel voltage to the gate electrode of the first PMOS TFT MP
1
. The first PMOS TFT MP
1
is turned on by the pixel voltage charged in the first capacitor C
1
, to thereby apply a supply voltage VDD from a voltage supply line VDDL, via the first node N
1
, to the EL cell OLED. At this time, a channel width of the first PMOS TFT MP
1
is varied depending on the voltage level of the pixel signal to control an amount of current applied to the EL cell OLED. Accordingly, the EL cell OLED generates light corresponding to the current amount applied from the first PMOS TFT MP
1
.
The second PMOS TFT MP
2
responds to a gate signal GLS, as shown in
FIG. 3
, applied from the gate line GL to selectively connect the second node N
2
to the EL cell OLED. More specifically, the second PMOS TFT MP
2
connects the second node N
2
to the EL cell OLED at a time interval when the gate signal GLS is enabled at a low logic, to thereby charge the pixel signal into the capacitor C
1
. In other words, the second PMOS TFT MP
2
forms a current path of the first capacitor C
1
at a time interval when the gate signal GLS at the gate line GL is enabled.
The capacitor C
1
charges a pixel signal at the enabling interval of the gate signal GLS and allows a voltage at the gate electrode of the first PMOS TFT MP
1
to go lower than a voltage at the drain electrode thereof by the voltage level of the charged pixel signal. Thus, the first PMOS TFT MP
1
controls its channel width depending on the voltage level of the pixel signal, to thereby determine the current amount flowing from the first node N
1
into the EL cell OLED.
The cell driving circuit
16
in
FIG. 2
further includes a third PMOS TFT MP
3
responding to a gate signal GLS at the gate line GL, and a fourth PMOS TFT MP
4
responding to an inverted gate signal /GLS from the gate bar line /GL.
The third PMOS TFT MP
3
is turned on at a time interval when a low logic of the gate signal GLS is applied from the gate line GL, to thereby connect the capacitor C
1
connected to the first node N
1
and the drain electrode of the first PMOS TFT MP
1
to the data line DL. In other words, the third PMOS TFT MP
3
plays the role of sending a pixel signal at the data line DL to the first node N
1
in response to a low logic of gate signal GLS. As a result the third PMOS TFT MP
3
is turned on at a time interval when the gate signal GLS at the gate line GL remains at a low logic, to thereby charge the pixel signal into the capacitor C
1
connected between the first and second nodes N
1
and N
2
.
The fourth PMOS TFT MP
4
is turned on at a time interval when a low logic of the inverted gate signal /GLS from the gate inverting line /GL is applied to the gate electrode thereof, to thereby connect the first node N
1
to which the capacitor C
1
and the drain electrode of the first PMOS TFT MP
1
have been connected, to the voltage supply line VDDL. At a time interval when the fourth PMOS TFT MP
4
has been turned on, a supply voltage VDD at the voltage supply line VDDL is applied to the EL cell OLED, via the first node N
1
and the first PMOS TFT MP
1
. Thus, the EL cell OLED generates light corresponding to an amount of the voltage level of the pixel signal.
The EL panel as mentioned above receives the current required for generating light using the EL cell OLED from the PMOS TFT. Such a characteristic of the PMOS TFT is as shown in FIG.
4
.
Referring to
FIG. 4
, the characteristic of the PMOS TFT shows that a voltage VDS between the drain electrode and the source electrode and a drain current ID differs depending on a value of a gate voltage VG applied to the gate electrode. Particularly, in the EL panel, a control of the current is most important because light emission amount varies depending on an amount of the current.
A current applied to the EL cell OLED increases until it reaches a threshold voltage VTH of the PMOS TFT like portion ‘A’ indicated by the dotted lines in
FIG. 4
, with respect to a small variation of the voltage VDS between the drain electrode and the source electrode. As a result, there is a problem in that vertical and horizontal stripes occur at a video image displayed on the EL panel.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to an electro-luminescence panel that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An advantage of the present invention is to provide an electro-luminescence panel that is capable of improving brightness.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages of the invention, an electro-luminescence panel according to one embodiment of the present invention includes a first electro-luminescence cell driving circuit arranged at a crossing of a first gate line and a

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