Electro-luminescence panel

Details Electro-luminescence panel Electro-luminescence panel

2002-06-19

2004-02-10

Philogene, Haissa (Department: 2821)

Electric lamp and discharge devices: systems

Plural power supplies

Plural cathode and/or anode load device

C315S169300, C345S204000, C345S048000, C345S076000, C257S314000, C257S368000

Reexamination Certificate

active

06690115

ABSTRACT:

This application claims the benefit of Korean Patent Application No. 2001-35662, filed on Jun. 22, 2001, which is hereby incorporated by reference for all purposes as if fully set forth herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an electro-luminescence display (ELD), and more particularly to an electro-luminescence panel that is capable of improving a picture quality.
2. Discussion of the Related Art
Recently, there have been developed various flat panel display devices reduced in weight and bulk that are capable of eliminating disadvantages associated with cathode ray tubes (CRTs). Such flat panel display devices include a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP) and an electro-luminescence (EL) panel, etc.
Studies for heightening a display quality of the flat panel display device and for providing the flat panel display with a large-scale screen have been actively made. The EL panel in such display devices is a self-emission device. The EL panel excites a fluorescent material using carriers such as electrons and holes, etc. to display a video image. The EL panel has advantages in that a low direct current voltage driving is possible and a response speed is fast.
As shown in
FIG. 1
, such an EL panel includes gate lines GL and data lines DL arranged in such a manner to cross each other, and pixel elements
108
arranged at crossings between the gate lines GL and the data lines DL. Each of the pixel elements
108
is driven when a gate signal on the gate line GL is enabled, thereby generating light corresponding to the amount of current of the pixel signal on the data line DL.
Further, the EL panel
104
includes current drivers
106
connected to the data lines DL. Each of the current drivers
106
control the current flowing from pixel elements
108
, via the data line DL, into itself in response to a pixel signal, thereby applying the pixel signal to each pixel element
108
. The current driver
106
allows electric charge current to flow in the pixel elements
108
. A current signal which changes in accordance with the pixel signal flows in the pixel elements
108
with the aid of the current driver
106
.
The gate lines GL of the EL panel
104
is connected to a gate driver
100
while the current drivers
106
are connected to the data driver
102
. The gate driver
100
sequentially drives the gate lines GL. The data driver
102
applies pixel voltage signals for one line to the current drivers
106
. Each of the current drivers
106
converts a pixel voltage signal from the data driver
102
into a backward pixel current signal, and applies the converted pixel current signal to the pixel element
108
. In other words, the current driver
106
controls the amount of current on a current path going through the data line DL from the pixel element
108
, thereby increasing a maximum amount of current at the pixel element
108
and a difference in the amount of current according to a gray scale level. As a result, the EL panel
104
is capable of displaying a gray scale picture.
Referring to
FIG. 2
, the pixel element
108
includes an EL cell (ELC) connected to a first low voltage line FVL, and an EL cell driving circuit
110
connected between the EL cell (ELC) and the data line DL. The first low voltage line FVL can be connected to a ground voltage source GND, or to the first low voltage source generating a negative voltage. The EL cell driving circuit
110
applies a forward current signal which changes in accordance with a backward amount of current on the data line DL to the EL cell (ELC) in a time interval when a gate signal on the gate line GL is enabled. To this end, the EL cell driving circuit
110
includes third and fourth PMOS TFTs Q
3
and Q
4
connected to form a current mirror among the EL cell (ELC), a first node N
1
and a supply voltage line VDDL, and a capacitor C connected to a second node N
2
to which gate electrodes of the third and fourth PMOS TFTs Q
3
and Q
4
are commonly connected and the supply voltage line VDDL.
The capacitor C charges a signal current on the data line DL when the supply voltage line VDDL is connected to the data line DL, and applies the charged signal current to the gate electrodes of the third and fourth PMOS TFTs Q
3
and Q
4
. The third PMOS TFT Q
3
is turned on by a signal current charged in the capacitor C, thereby applying a supply voltage VDD on the supply voltage line VDDL to the EL cell (ELC). At this time, the third PMOS TFT Q
3
varies its channel width depending upon an amount of signal current charged in the capacitor C, thereby controlling the amount of current coupled from the supply voltage line VDDL to the EL cell (ELC). Then, the EL cell (ELC) generates light corresponding to the amount of current applied, via the third PMOS TFT Q
3
, from the supply voltage line VDDL. The fourth PMOS TFT Q
4
also controls the current flowing from the supply voltage line VDDL into the data line DL to thereby determine the amount of current flowing into the EL cell (ELC) via the third PMOS TFT Q
3
.
Further, the EL cell driving circuit
110
includes first and second PMOS TFTs Q
1
and Q
2
which commonly respond to the gate signal on the gate line GL. The first PMOS TFT Q
1
is turned on in a time interval when a low logic of gate signal is applied from the gate line GL, thereby connecting a source electrode of the first PMOS TFT Q
1
connected to the first node N
1
to the data line DL. In other words, the first PMOS TFT Q
1
plays the role of forming a current path extending from the supply voltage line VDDL, via the fourth PMOS transistor Q
4
, the first node N
1
and itself, into the data line DL in response to the low logic gate signal. The second PMOS TFT Q
2
is also turned on in a time interval when the low logic gate signal from the gate line GL is applied to a gate electrode thereof, thereby connecting the gate electrodes of the third and fourth PMOS TFTs Q
3
and Q
4
, via the second node N
2
and the first node N
1
connected to one terminal of the capacitor C, to the data line DL. In other words, the first and second PMOS TFTs Q
1
and Q
2
is turned on in a time interval when the gate signal on the gate line GL remains at a low logic to connect the data line DL to the supply voltage line VDDL as well as the second node N
2
, thereby charging a charge amount (or a signal current) corresponding to the amount of current flowing in the data line DL.
The first PMOS TFT Q
1
of such an EL cell driving circuit
110
is turned on simultaneously with the second PMOS TFT Q
2
having the same threshold voltage when the gate signal is changed from a low logic into a high logic. Thus, a kick-back phenomenon occurs in which a charge amount charged in the capacitor C is leaked at the falling edge of the gate signal. As a result, the EL cell (ELC) fails to accurately generate light corresponding to the amount of current on the data line DL, thereby causing picture deterioration or distortion.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to an electro-luminescence pixel that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An advantage of the present invention to provide an electro-luminescence panel that is capable of improving picture quality.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, an electro-luminescence panel according to one embodiment of the present invention includes a plurality of gate lines; a plurality of data lines crossing the gate lines; a

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