Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – Plural inputs
Patent
1997-09-16
2000-02-29
Strecker, Gerard
Electricity: measuring and testing
Measuring, testing, or sensing electricity, per se
Plural inputs
324111, 324117H, G01R 21133, G01R 2108
Patent
active
060313692
DESCRIPTION:
BRIEF SUMMARY
The present invention relates to an electricity meter and method of metering.
BACKGROUND OF THE INVENTION
In an Alternating Current (A.C.) ENERGY (J) meter a signal proportional to instantaneous POWER (W) is applied to an INTEGRATOR which outputs a pulse whenever a predetermined unit of energy is measured. The following equations apply: ##EQU1##
FIG. 1 (prior art) shows a typical example of the instantaneous power signal derived from the multiplication of voltage and current signals.
This instantaneous power signal IP as shown in FIG. 1 (prior art) is then typically applied to the input of an integrator as shown in FIG. 2 (prior art). This integrator comprises a capacitor C, a Window Comparator, pulse generation logic and a capacitor discharge switch S.
The power input signal IP is applied to the capacitor C. The capacitor C either charges or discharges to one of two thresholds of the window comparator. If the upper threshold of the window comparator is reached the positive output `.+-.` of the comparator is activated. The Pulse logic circuit outputs a pulse to indicate a unit of forward energy and closes switch S for a set period of time to discharge the capacitor C. Switch S is opened and the process repeats. If the lower threshold of the window comparator is reached the negative output `-` of the comparator is activated. The Pulse logic circuit outputs a pulse to indicate a unit of reverse energy and closes switch S for a set period of time to discharge the capacitor C. Switch S is opened and the process repeats.
One of the disadvantages of this approach is that Direct Current (D.C.) offsets on the IP power signal caused by circuit offsets add or subtract from the measured energy causing system measurement errors. Another disadvantage is the need to use a very low leakage capacitor for the integrating capacitor C to reduce measurement errors caused by the self discharge characteristics of the capacitor. This usually restricts the use of capacitors integrated with the circuit into a silicon chip. One other disadvantage of this approach is the time taken to discharge the capacitor after a unit of energy has been measured again leading, to overall measurement errors.
SUMMARY OF THE INVENTION
The invention preferably provides an electricity meter operative to receive a mains A.C. signal and a first A.C. signal the magnitude of which is dependent on the flow of electrical power through a conductor, comprising a first pulse generating means operative to provide pulses at a rate proportional to the magnitude of the first A.C. signal whilst the mains A.C. signal is positive and a second pulse generating means operative to provide further pulses at a rate proportional to the magnitude of the first A.C. signal whilst the mains A.C. signal is negative the meter including accumulator means to determine from the pulses a first pulse count for the periods whilst the product of the first A.C. signal and the mains A.C. signal is positive and a second pulse count for the periods whilst the product of the first A.C. signal and the mains A.C. signal is negative, the pulse counts providing a measure of energy conducted. The first A.C. signal is an A.C. current signal or an A.C. voltage signal preferably provided by a Hall sensor. The mains A.C. signal is preferably an A.C. mains voltage signal.
The present invention in a preferred embodiment overcomes the above mentioned disadvantages of the prior art. Also, its advantage allows the electronic circuity and integrator capacitor(s) to be integrated into a silicon chip.
The pulse signals are preferably provided by the first A.C. signal being directed selectably to the first or second pulse generating means. The first pulse generating means is preferably an integrator circuit preferably comprising a first capacitor connected via a first pulse generator to a first accumulator. The second pulse generating means is preferably an integrator circuit preferably comprising a second capacitor connected via a second pulse generator to a second accumulator. When a capacitor is cha
REFERENCES:
patent: 3747605 (1973-07-01), Cook
patent: 3955138 (1976-05-01), Milkovic
patent: 4224671 (1980-09-01), Sugiyama et al.
patent: 4525669 (1985-06-01), Holberton et al.
patent: 4749941 (1988-06-01), Halder et al.
patent: 4972141 (1990-11-01), Rozman et al.
Horstmann Timers & Controls Limited
Strecker Gerard
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