Electricaly erasable and programmable read only memory with a di

Details Electricaly erasable and programmable read only memory with a di Electricaly erasable and programmable read only memory with a di

1989-12-11

1992-08-11

Popek, Joseph A.

Static information storage and retrieval

Floating gate

Particular biasing

36518909, 365204, 365233, 3652335, G11C 1604, G11C 700

Patent

active

051385759

ABSTRACT:
An electrically erasable and programmable read only memory includes a memory cell array having a plurality of memory cells coupled to bit lines and word lines. Each of the memory cells includes a select transistor controlled by one of the word lines, a memory transistor of the enhancement type coupled to one of the bit lines through the select transistor and having a control gate, and a drive transistor having a gate coupled to the one of the word lines and applying a control gate voltage supplied through a program line to the control gate of the memory transistor. Further, the electrically erasable and programmable read only memory includes a select device for selecting at least one of the bit lines and one of the word lines on the basis of an address supplied from an external device, and a sense amplifier for outputting data stored in the memory cell array. Also provided is a discharging device which discharges the drain regions and the control gates of the memory transistors after a predetermined time has passed from a transition of the address and application of the control gate voltage.

REFERENCES:
patent: 4279024 (1981-07-01), Schrenk
patent: 4677590 (1987-06-01), Arakawa
patent: 4719603 (1988-01-01), Shinagawa et al.
patent: 4727519 (1988-02-01), Morton et al.
patent: 4807003 (1989-02-01), Mohammadi et al.
patent: 4835742 (1989-05-01), Schrenk
patent: 4905197 (1990-02-01), Urai

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