Electrically rewritable nonvolatile semiconductor memory device

Details Electrically rewritable nonvolatile semiconductor memory device Electrically rewritable nonvolatile semiconductor memory device

2007-09-04

2007-09-04

Phung, Anh (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185250

Reexamination Certificate

active

11246215

ABSTRACT:
A clamp circuit is connected to one-side ends of first and second bit lines which are adjacent in a memory cell array and a data cache is connected to the other ends thereof. The first and second bit lines are selectively divided into plural portions by use of first and second switching elements. The data cache, clamp circuit and first and second switching elements are controlled by use of a control circuit and the bit line to which a memory cell of an address to be written is connected is precharged by use of the clamp circuit or data cache and the other bit line is shielded by the clamp circuit.

REFERENCES:
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patent: 6751126 (2004-06-01), Kim
patent: 2005/0286302 (2005-12-01), O
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patent: 2006/0140013 (2006-06-01), Maejima et al.
patent: 4-276393 (1992-10-01), None

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