Electrically reprogrammable non volatile memory

Details Electrically reprogrammable non volatile memory Electrically reprogrammable non volatile memory

1979-02-22

1980-10-14

Hecker, Stuart N.

Static information storage and retrieval

Floating gate

Particular biasing

365181, G11C 1140

Patent

active

042285275

ABSTRACT:
An electrically reprogrammable non-volatile memory device is disclosed which includes complementary MOS transistors provided with a polycrystalline silicon floating gate electrode in a common n.sup.- -type substrate. The device comprises three main parts. The first part, which is used for writing, comprises a p-channel writing transistor, a p-channel control transistor and a resistance element. The second part, which comprises a second gate electrode capacitance coupled with the floating gate, is used for erasing. The third part is used for performing information read-out and consists of a p-channel transistor the gate of which forms a portion of the floating gate and the drain of which is connected to a read-out terminal and to the terminal of a loading element having its other terminal connected to a negative supply potential. This device enables writing control to be performed using a logical signal of the order of one volt, read-out being also performed with a low voltage value, with low energy consumption. Erasure of information can be performed electrically and the retention time is of several years.

REFERENCES:
Gosney, DIFMOS-A Floating-Gate Electrically Erasable Nonvolatile Semiconductor Memory Technology, IEEE Trans. on Electron Devices, vol. ED-24, No. 5, 5/77, pp. 594-599.
Rossler et al., Erasable and Electrically Reprogrammable Read-Only Memory Using the N-Channel SIMOS One-Transistor Cell, Siemens Forschungsund Entwicklungsberichten, vol. 4, No. 6, 1975, pp. 345-362.
Tarvi et al., Electrically Reprogrammable Nonvolatile Semiconductor Memory, IEEE Jour. of Solid-State Circuits, vol. SC-7, No. 5, 10/72, pp. 369-375.

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