Electrically-programmable transistor antifuses

Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S050000, C257S798000

Reexamination Certificate

active

10780427

ABSTRACT:
Integrated circuit antifuse circuitry is provided. A metal-oxide-semiconductor (MOS) transistor serves as an electrically-programmable antifuse. The antifuse transistor has source, drain, gate, and substrate terminals. The gate has an associated gate oxide. In its unprogrammed state, the gate oxide is intact and the antifuse has a relatively high resistance. During programming, the gate oxide breaks down, so in its programmed state the antifuse transistor has a relatively low resistance. The antifuse transistor can be programmed by injecting hot carriers into the substrate of the device in the vicinity of the drain. Because there are more hot carriers at the drain than at the substrate, the gate oxide is stressed asymmetrically, which enhances programming efficiency. Feedback can be used to assist in turning the antifuse transistor on to inject the hot carriers.

REFERENCES:
patent: 4207556 (1980-06-01), Sugiyama et al.
patent: 4306185 (1981-12-01), Leuschner
patent: 4433331 (1984-02-01), Kollaritsch
patent: 4609986 (1986-09-01), Hartmann et al.
patent: 4617479 (1986-10-01), Hartmann et al.
patent: 4642487 (1987-02-01), Carter
patent: 4761768 (1988-08-01), Turner et al.
patent: 5070384 (1991-12-01), McCollum et al.
patent: 5291434 (1994-03-01), Kowalski
patent: 5303199 (1994-04-01), Ishihara et al.
patent: 5324681 (1994-06-01), Lowrey et al.
patent: 5374832 (1994-12-01), Tung et al.
patent: 5463244 (1995-10-01), De Araujo et al.
patent: 5510730 (1996-04-01), El Gamal et al.
patent: 5831923 (1998-11-01), Casper
patent: 5844298 (1998-12-01), Smith et al.
patent: 5925915 (1999-07-01), Liu et al.
patent: 6087707 (2000-07-01), Lee et al.
patent: 6108261 (2000-08-01), Kim et al.
patent: 6125069 (2000-09-01), Aoki
patent: 6130469 (2000-10-01), Bracchitta et al.
patent: 6433395 (2002-08-01), Hsu
patent: 6441438 (2002-08-01), Shih et al.
patent: 6456546 (2002-09-01), Kim et al.
patent: 6466423 (2002-10-01), Yu
patent: 6477094 (2002-11-01), Kim et al.
patent: 6897543 (2005-05-01), Huang et al.
patent: 2001/0050407 (2001-12-01), Gelsomini et al.
patent: 2002/0050625 (2002-05-01), Cutter et al.
patent: 2002/0074602 (2002-06-01), Lin et al.
patent: 2003/0169095 (2003-09-01), Kothandaraman
patent: 2003/0173622 (2003-09-01), Porter et al.
patent: 2004/0065941 (2004-04-01), Marr
patent: 2004/0114433 (2004-06-01), Forbes
patent: 2005/0185351 (2005-08-01), Miller et al.
U.S. Appl. No. 10/646;013, Cheng H. Huang et al.
Wei Zhang et al., “Energy Effect of the Laser-Induced Vertical Metallic Link”, IEEE Transactions on Semiconductor Manufacturing, vol. 14, No. 2, May 2001 pp. 163-169.
“Analyzing the process window for laser copper-link processing” Solid State Technology—Semiconductor manufacturing and wafer fabrication, Jan. 8, 2003.
Alexander Kalnitsky et al. “CoSi2 integrated fuses on poly silicon for low voltage 0.18 um CMOS applications” (c) 1999 IEEE.
Mohsen Alavi “A PROM Element Based on Salicide Agglomeration of Poly Fuses in a CMOS logic process” IEEE International Electron Devices Meeting, Dec. 1997.
Noriaki Sato et al. “A New Programmable Cell Utilizing Insulator Breakdown”, IEDM 1985, pp. 639-642.
Jinbong Kim et al. “Three-Transistor One-Time Programmable (OTP) ROM Cell Array Using Standard CMOS Gate Oxide Antifuse”, IEEE Electron Device Letters, vol. 24, No. 9, Sep. 2003 pp. 589-591.
Wei Zhang et al. “Laser-Formed Vertical Metallic Link and Potential Implementation in Digital Logic Integration”, PROC MAPLD, MD, 1999 pp. 1-7 (B5).
Wei Zhang et al., “Reliability of laser-induced metallic vertical links,” IEEE Trans. on Advanced Packaging, pp. 614-619 Nov. 1999 vol. 22 Issue 4.
JB Bernstein et al. “Analysis of laser metal-cut energy process window” IEEE Trans. on Semicond. Manuf., pp. 228-234, May 2000, vol. 13, Issue 2.
JB Bernstein et al. “Laser energy limitation for buried metal cuts” IEEE Electron Device Letters, pp. 4-6, Jan. 1998, vol. 19, Issue 1.
RT Smith et al. “Laser programmable redundancy and yield improvement in a 64 K DRAM”, IEEE Journal of Solid-State Circuits, pp. 506-514 Oct. 1981, vol. 16, Issue 5.
V. Klee et al. “A 0.13 um logic-based embedded DRAM technology with electrical fuses, Cu interconnect in SiLK, sub-7ns random access time and its extension to the 0.10 um generation,” IEEE (c) 2001 IEDM (International Electron Devices Meeting), Technical Digest, pp. 18.5.1-18.5.4.
M. Depas et al. “Soft Breakdown of Ultra-Thin Gate Oxide Layers” IEEE Transactions on Electron Devices IEEE (c) 1996, vol. 43, No. 9, Sep. 1996 pp. 1499-1504.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Electrically-programmable transistor antifuses does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Electrically-programmable transistor antifuses, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electrically-programmable transistor antifuses will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3812912

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.