Electrically programmable ROM

Details Electrically programmable ROM Electrically programmable ROM

1988-11-09

1989-06-06

Fears, Terrell W.

Static information storage and retrieval

Floating gate

Particular biasing

36518907, 365226, 371 21, 324 73AT, 324158R, G11C 1134, G11C 2900, G01R 1512

Patent

active

048377422

ABSTRACT:
An electrically programmable ROM is provided for avoiding frauds by producing, internally in the memory, the different potentials which it uses for verifying the memory points chosen. The verification of writing of information in a point is obtained by subjecting this point to a calibrated selection voltage, to which an external operator cannot have access. This calibrated voltage is produced by a multiplying generator. This latter feeds into one or more calibrators for producing all the useful voltages. Reading and writing orders are then given to a switching circuit which causes the corresponding application of these calibrated voltages. An external operator cannot enter in the memory level falsified signals for modifying the meaning of the contents of the recorded information.

REFERENCES:
patent: 4253059 (1981-02-01), Fairchild
patent: 4460982 (1984-04-01), Intel
patent: 4597060 (1986-06-01), Mitchell et al.
patent: 4656607 (1987-04-01), Hagawara et al.
patent: 4672580 (1987-06-01), Yau et al.
patent: 4709350 (1987-11-01), Nakagome et al.
patent: 4727515 (1988-02-01), Hsu
Patents Abstracts of Japan, vol. 1, No. 159, Dec. 16, 1977 p. 859E77 & JP A, 52101934 (Tokyo Shibaura Denki K.K.) Aug. 26, 1977.
Patent Abstracts of Japan, vol. 5, No. 107 (P-70) (779) Jul. 11, 1981 & JP A, 5651090 (Tokio Shibaura Denki K.K.) May 8, 1981 See Abstract.
IEEE Transactions on Electron Devices, vol. ED-27, No. 7, Jul. 1980 IEEE New York (U.S.) B. Gerber et al: "Low-Voltage Single Supply CMOS Electrically Erasable Read-Only Memory", pp. 1211-1216 See p. 1214, FIG. 8.

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