Static information storage and retrieval – Read only systems – Resistive
Patent
1981-02-23
1984-04-10
Fears, Terrell W.
Static information storage and retrieval
Read only systems
Resistive
365 96, 365105, 365175, G11C 1140, G11C 1136
Patent
active
044425074
ABSTRACT:
In the disclosed memory, address decode means are integrated into a surface of a substrate, for addressing cells in the memory; an insulating layer covers the address decode means and the substrate; an array of spaced-apart memory cell select lines lie on the insulating layer; and outputs from the address decode means respectively couple through the insulating layer to the select lines. Each cell of the memory is comprised of a pair of the select lines and further includes a resistive means between that pair which irreversibly switches from a relatively high resistance state to a relatively low resistance state upon the application of a threshold voltage thereacross, and the resistance states are representative of the information in the cell.
REFERENCES:
patent: 3245051 (1966-04-01), Robb
patent: 3529299 (1970-09-01), Chung et al.
patent: 3582908 (1971-06-01), Koo
patent: 3641516 (1972-02-01), Castrucci et al.
patent: 3735367 (1973-05-01), Bennett, Jr.
patent: 4064493 (1977-12-01), Davis
patent: 4122547 (1978-10-01), Schroeder et al.
patent: 4152627 (1979-05-01), Priel
patent: 4185321 (1980-01-01), Iwahashi
patent: 4287569 (1981-09-01), Fukushima
Burroughs Corporation
Fassbender Charles J.
Fears Terrell W.
Peterson Kevin R.
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