Patent
1977-07-05
1979-03-20
Edlow, Martin H.
357 28, 357 35, 357 86, H01L 6710, H01L 2356
Patent
active
041457021
ABSTRACT:
A matrix of columns and rows of conductors with transistors located at the intersection thereof on a semiconductor chip is formed utilizing the washed emitter process which locates the ohmic contact windows close to the PN junction so that a small size piece of free metal, i.e., not connected to any other conductor, may be located within a short distance, i.e., one micron or less, to the PN junction selected to be fused during the programming of a Read Only Memory. The small size of the free metal as near as possible to this PN junction minimizes heat losses, reduces power consumption and reduces programming errors normally incurred in the programming of Read Only Memories.
REFERENCES:
patent: 3641516 (1972-02-01), Castrucci et al.
patent: 3733690 (1973-05-01), Rizzi
patent: 3742592 (1973-07-01), Rizzi
patent: 3783048 (1974-01-01), Sanders
patent: 3848238 (1974-11-01), Rizzi
patent: 3971058 (1976-07-01), Fagan
Kabell Louis J.
Muller Harold H.
Rau, III John W.
Tam Richard K. W.
Burroughs Corporation
Dwyer Joseph R.
Edlow Martin H.
Peterson Kevin R.
Young Mervyn L.
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