Static information storage and retrieval – Floating gate – Disturbance control
Patent
1992-09-30
1998-02-17
Gossage, Glenn
Static information storage and retrieval
Floating gate
Disturbance control
36518517, 36518518, 36523006, G11C 1604, G11C 1606, G11C 702
Patent
active
057198055
ABSTRACT:
A semiconductor memory includes memory cells divided into a plurality of a series circuit units arranged in matrix fashion and comprising a plurality of memory cells connected in series. The memory cells each consist of a non-volatile transistor having a control gate electrode, a floating gate electrode and an erase gate electrode, and may comprise EEPROM cells. One end of each series circuit unit is coupled to a bit line with the circuit units in a given column of circuit units being coupled to the same bit line. Row lines are provided wherein each circuit unit in a given row of circuit units has the control gate electrodes of its memory cells coupled to a row line, the control gate electrodes of each memory cell in a given row of memory cells being connected to a common row line. A voltage by which a selected non-volatile transistor is driven to its saturation state is applied to the control gate electrode of the selected transistor through the corresponding row line. Another voltage is applied to the control gate electrodes of the remaining non-selected non-volatile transistors of the series circuit unit. A ground voltage, or zero volts, may be applied to the row, lines in certain non-selected circuit units.
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Gossage Glenn
Kabushiki Kaisha Toshiba
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