Static information storage and retrieval – Floating gate – Multiple values
Patent
1998-06-23
1999-09-07
Nelms, David
Static information storage and retrieval
Floating gate
Multiple values
36518521, 36518519, 36518518, G11C 1134
Patent
active
059497092
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
This invention relates to an electrically programmable memory, and particularly, though not exclusively, to an electrically erasable programmable read-only memory (EEPROM or E.sup.2 PROM).
BACKGROUND OF THE INVENTION
In the field of memories generally and E.sup.2 PROMs in particular there is constant demand for shrinking geometries, increasing densities and hence reducing die. costs. However, because E.sup.2 PROM involves high voltages, certain physical breakdown effects limit the scaling of the E.sup.2 PROM cell so it cannot be shrunk as per standard 5 V logic gates.
Conventionally, E.sup.2 PROM memory cells have stored binary values, i.e. either a `0` or a `1`. In efforts to increase storage density, two schemes have been proposed for multilevel cell systems:
Firstly it has been proposed to use a large double-polysilicon cell with a number of different sized control gates, allowing the programming of multi-level values into the cell by varying the coupling capacitance ratio of the cell. However, this multi-level scheme has the drawback that it requires a very large cell, hence producing no overall density benefits.
Secondly it has been proposed to program different values into a standard Flash EEPROM cell using a number of short programming bursts, the number of bursts controlling the threshold voltage of the cell, i.e. the value to be programmed; a complex multi-reference-level comparator must be used as a sense amplifier. However, this multi-level scheme has the drawback that, although the cell itself may be small, it requires a complex sense amplifier scheme with many accurate voltage levels being necessary.
SUMMARY OF THE INVENTION
In accordance a first aspect of the invention there is provided an electrically programmable memory as claimed in claim 1.
In accordance with a second aspect of the invention there is provided a method of programming an electrically programmable memory as claimed in claim 7.
In accordance with a third aspect of the invention there is provided a method of reading an electrically programmed memory as claimed in claim 8.
BRIEF DESCRIPTION OF THE DRAWINGS
One E.sup.2 PROM cell in accordance with a preferred embodiment of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which:
FIG. 1 is a schematic circuit diagram of an E.sup.2 PROM cell used in the present invention;
FIG. 2 is a cross-sectional view of part of the cell of FIG. 1;
FIG. 3 is a schematic circuit diagram of an E.sup.2 PROM cell used in the present invention and incorporating additional circuitry for reading programmed cell data using a static, iterative sensing scheme; and
FIG. 4 is a schematic circuit diagram of an E.sup.2 PROM cell used in the present invention and incorporating additional circuitry for reading programmed cell data using a dynamic sensing scheme.
DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT
Referring firstly to FIG. 1, in a typical standard E.sup.2 PROM cell array, an E.sup.2 PROM cell 10 includes a field-effect transistor metal-oxide-semiconductor (FETMOS) double-polysilicon structure 12 with a floating gate as the charge storage region. In order to allow the cell 10 to be individually addressed in the array, the cell also includes an addressing FETMOS transistor 14. The source electrode of the transistor 12 is connected to an "array ground" node AG, and the gate electrode of the transistor 12 is connected to a "control gate" node CG. The drain electrode of the transistor 12 is connected to the source electrode of the transistor 14. The drain electrode of the transistor 14 is connected to a "bit line" node BL, and the gate electrode of the transistor 14 is connected to a "word/row line" node WL.
Referring now particularly to FIG. 2, the transistor 12 has a substrate region 12.1 of p- type silicon, and drain and source regions 12.2, 12.3 of n+ type silicon. The transistor 12 also has a floating gate 12.4 of a first polysilicon material overlaid by a control gate 12.5 of a second polysilicon
REFERENCES:
patent: 5218571 (1993-06-01), Norris
patent: 5629890 (1997-05-01), Engh
Dover Rennie William
Motorola Inc.
Nelms David
Nguyen Vanthu
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