Electrically programmable memory matrix

Details Electrically programmable memory matrix Electrically programmable memory matrix

1983-07-28

1986-06-24

Popek, Joseph A.

Static information storage and retrieval

Addressing

365189, 365185, G11C 800

Patent

active

045970645

ABSTRACT:
An electrically programmable memory matrix comprises electrically programmable memory cells arranged in columns and rows, each consisting of a source-drain series arrangement of a memory transistor with a select transistor. The gate of the select transistor may be connected to one of row selecting lines of a row decoder, to which there are connected all gates of one row of the selected transistors of the memory cells of the same row. Control gates of groups of memory transistors (Ts) of one row may be connected to one common programming line, with these programming lines being connected by blocks via each time one group select transistor to one common block line which, via the source-drain line of a block select transistor whose gate is connected to one of a plurality of outputs of a block decoder is connected to one source of block signals. Re-programmability of a fixed number of memory cells only upon application of a further input signal, apart from a function signal, is accomplished by subdividing at least one of the two decoders into a first decoder part to the function signal input of which the programming signal is applied directly, and into a second decoder part whose function signal input is connected to the output of a gate circuit having two inputs. Th output signal of the gate circuit is only then at the value corresponding to the function "programming" when the first input is also at the value corresponding to the function "programming", and when the second input is at that particular value which permits a programming of the second decoder part.

REFERENCES:
patent: 4434478 (1984-02-01), Cook et al.

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