Electrically programmable memory cell

Details Electrically programmable memory cell Electrically programmable memory cell

1992-03-03

1997-06-17

Clawson, Jr., Joseph E.

Static information storage and retrieval

Floating gate

Particular connection

36518518, 36518527, 257315, 257318, 257320, G11C 1604

Patent

active

056403461

ABSTRACT:
An EPROM cell comprises an MOS device including a floating gate electrode overlying, and ohmically insulated from, the channel region of the MOS device, and a separate diode including a p-n junction having a substrate surface intercept. A floating gate electrode overlies the diode p-n junction intercept and is ohmically isolated therefrom by an intervening insulating layer. Writing of data into the floating gate electrode of the MOS device is achieved by causing a voltage breakdown across the diode p-n junction and the flow of high energy electrons across the junction. A voltage is simultaneously applied to the diode gate electrode thereby attracting some of the high energy electrons through the overlying insulating layer into the diode floating gate electrode. The diode gate electrode is ohmically connected to the MOS floating gate electrode on which some of the electrons are stored for affecting the turn-on, turn-off characteristics of the MOS device.

REFERENCES:
patent: 4035820 (1977-07-01), Matzen
patent: 4037242 (1977-07-01), Gosney
patent: 4305083 (1981-12-01), Gutierrez
patent: 4612629 (1986-09-01), Harari
patent: 4878199 (1989-10-01), Mitzutani
M. Kikuchi et al., "A 2048-Bit N-Channel Fully Decoded Electrically Writable/Erasable Nonvolatile Read Only Memory," 1st European Sol. St. Cirkts Conf.-Essire, Canterbury, England (2-5 Sep. 1975), pp. 66-67.
K. Yashikawa et al., "An Eprom Cell Structure for EPLD's Compatible With Single Poly-Si Gate Process,"IEEE Trans. on Elec. Dev., vol. 37 #3, Mar. 1990, pp. 675-679.

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