Electrically-programmable low-impedance anti-fuse element

Details Electrically-programmable low-impedance anti-fuse element Electrically-programmable low-impedance anti-fuse element

1987-12-28

1990-02-06

Larkins, William D.

357 59, 357 236, 357 54, H01L 2702, H01L 2986

Patent

active

048992054

ABSTRACT:
Electrically-programmable low-impedance anti-fuses are disclosed having capacitor-like structure with very low leakage before programming and a low resistance after programming. The electrically-programmable low-impedance anti-fuses of the present invention include a first conductive electrode which may be formed as a diffusion region in a semiconductor substrate or may be formed from a semiconductor material, such as polysilicon, located above and insulated from the substrate. A dielectric layer, which, in a preferred embodiment includes a first layer of silicon dioxide, a second layer of silicon nitride and a third layer of silicon dioxide, is disposed over the first electrode. A second electrode is formed over the dielectric layer from a semiconductor material such as polysilicon, or a metal having a barrier metal underneath. At least one of the two electrodes of each anti-fuse is highly-doped or implanted with arsenic such that high concentrations of arsenic exist at the interface between the electrode and the dielectric layer. This arsenic will combine with other material and flow into the anti-fuse filament after programmed to form a low resistance controllable anti-fuse link. Circuitry is provided which allows the anti-fuse of the present invention to be programmed by application of a suitable programming voltage to input-output pins of the integrated circuit containing the anti-fuse. Where more than one anti-fuse is to be programmed using the programming voltage applied at the input-output terminals, other additional input-output terminals may serve as address inputs to specify the anti-fuse to be programmed.
In another embodiment of the present invention a programmable read-only memory array comprised of memory cells including an anti-fuse in combination with a single transistor. X-address and Y-address decoder circuits are provided to both program and read the contents of any selected memory cell in the array.

REFERENCES:
patent: 2784389 (1957-03-01), Kelly
patent: 3423646 (1969-01-01), Cubert et al.
patent: 3576549 (1981-04-01), Hess et al.
patent: 3634929 (1972-01-01), Yoshida et al.
patent: 3742592 (1973-07-01), Rizzi et al.
patent: 4127900 (1978-11-01), Raffel et al.
patent: 4257832 (1981-03-01), Schwabe et al.
patent: 4322822 (1982-03-01), McPherson
patent: 4488262 (1984-12-01), Basire et al.
patent: 4494135 (1985-01-01), Moussie
patent: 4499557 (1985-02-01), Holmberg et al.
patent: 4507673 (1985-03-01), Aoyama et al.
patent: 4507756 (1985-03-01), McElroy
patent: 4507757 (1985-03-01), McElroy
patent: 4543594 (1985-09-01), Mohsen et al.

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