Electrically programmable logic array

Details Electrically programmable logic array Electrically programmable logic array

1986-03-31

1988-04-26

Fears, Terrell W.

Static information storage and retrieval

Read only systems

Semiconductive

365 94, 365103, G11C 1140

Patent

active

047409193

ABSTRACT:
An electrically programmable logic array (10) for binary signals having signal inputs A.sub.0 -A.sub.x) and signal outputs Q.sub.0 -Q.sub.i) comprises two row lines (a.sub.0,a.sub.0' -a.sub.x, a.sub.x') for each signal input. The signal applied to the signal input is generatable at the one row line in non-negated form and at the other row line in negated form. For each signal output a column line (q.sub.0 -q.sub.i) is provided.
In the non-programmable state between each row line and each column line there is an electrically conductive connection interruptable for the purpose of programming. Inserted into the connection between the signal inputs and each associated row line is a controllable switching member (S.sub.0,S.sub.0',-S.sub.x, S.sub.x') which is controllable by a control signal applied thereto in such a manner that its output signal changes with the signal applied to the associated signal input or irrespective of said signal always retains a predetermined signal value.

REFERENCES:
patent: 3721964 (1973-03-01), Barrett
patent: 4237547 (1980-12-01), Smith

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