Electrically programmable logic array

Details Electrically programmable logic array Electrically programmable logic array

1978-06-05

1979-12-04

Yusko, Donald J.

Communications: electrical

Digital comparator systems

307238, 365 63, 365189, G11C 502, G11C 1140

Patent

active

041774523

ABSTRACT:
A write once, read only electrically programmable storage circuit is disclosed, which employs a flip-flop circuit to store the programmed conductive state of the array device, by means of a blocking transistor connected between the array device and one node of the flip-flop, the control electrode of the blocking transistor being connected to the other node of the flip-flop. With the flip-flop having an initial first state so that the blocking device is conductive, a precharged signal may be conducted through the array device to ground indicating a first stored information state. By driving a write signal through the array device and the blocking device, of sufficient magnitude to set the flip-flop in its opposite state, the blocking device is then made nonconductive and subsequent attempts to transmit a precharge signal through the array device to ground, will not be possible, indicating a second stored information state. This basic storage circuit is inclined as the array cell in a programmable PLA chip architecture which requires only four additional pins beyond the mask programmable version. This is accomplished by the dual use of the output latches of the OR array for both reading out the array and for programming the array by a scan-in technique. Cells in the AND array are programmed by a product term programmer register which allows product terms to be programmed by input partitioning circuits.

REFERENCES:
patent: 3560764 (1971-02-01), McDowell
patent: 3936812 (1976-02-01), Cox et al.
patent: 4041459 (1977-08-01), Horninger
patent: 4094012 (1978-06-01), Perlegos et al.
patent: 4134151 (1979-01-01), O'Connell et al.

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