Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Patent
1997-06-06
1999-09-07
Martin-Wallace, Valencia
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
257209, H01L 2994
Patent
active
059491272
ABSTRACT:
In a multi-level interconnect structure, a fusible material fills an opening in an isolation layer disposed between two interconnect levels or between an interconnect level and a device layer. The opening which may be, for example, a contact hole or a via, may be fabricated using processes generally used to fabricate normally sized vias and contact holes. The opening has a cross-sectional area A reduced by a factor of x relative to normally sized openings. Because the fusible interlevel interconnection has a reduced cross-sectional area, a programming current develops a destructive programming current density within fusible interlevel interconnection while current densities in coupled conductors, including normally sized vias and contacts, remain within long term reliability limits. Read/write circuitry connected to the fusible interlevel interconnection supports the programming current and supports a read current. The read current is regulated such that a responsive current density in a nonprogrammed fusible interlevel interconnection does not exceed long term reliability limits.
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Hansen Anita M.
Lien Chuen-Der
Pilling David J.
Integrated Device Technology Inc.
Martin-Wallace Valencia
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