Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular signal path connections
Reexamination Certificate
1999-06-28
2001-12-25
Cao, Phat X. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular signal path connections
C257S529000, C257S530000
Reexamination Certificate
active
06333524
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor integrated circuits and more particularly to programmable fuse structures.
2. Description of the Related Art
Programmable circuits are well-known and incorporate a variety of programmable elements. One such programmable element is a fusible link whose conductivity is selectively altered. Fusible links are usually portions of a conductive layer which are unable to carry as much current as the remainder of the layer. In an unprogrammed state, the fusible link conducts with a very low impedance, approximately 2-6 ohms for metal fusible links, and serves as a low impedance current path between conductive bodies. In a programmed state, the fusible link becomes a virtual open circuit.
Fusible links are programmed in a number of different ways. For example, laser beams may effectively destroy and thus program selected fusible links. Additionally, programming circuitry may apply a voltage across a selected fusible link to produce a programming current in the fusible link sufficiently large to destroy the fusible link with time. Although some electrically programmed fusible links are recoverable by, for example, application of ultraviolet light, other fusible links are intended to be nonrecoverable, i.e. intended to be permanently nonconductive.
Fusible links may be used in conjunction with different types of integrated circuit structures. A fusible link such as fusible link
100
, illustrated in a top plan view in
FIG. 1
, labeled prior art, includes a conductive layer
102
which provides a low impedance current path between vias
104
and
106
. Conductive layer
102
includes a narrowed region or neck
108
where current density (i.e., current per unit area) increases relative to adjacent portions of conductive layer
102
. A properly fabricated narrowed region
102
conducts a nondestructive current in normal operations, such as a memory read operation. However, during programming, a programming voltage applied across vias
104
and
106
produces sufficiently high programming current density in neck
108
to melt neck
108
and create an open circuit between vias
104
and
106
.
Although fusible link
100
is well-known, a number of disadvantages exist relating to, for example, the ability to repeatedly fabricate the link, the ability to scale down the link to small geometries, the predictability of link performance, the large current required to program the link, and the ability to achieve desired packing densities with the link. For example, the formation of fusible link
100
generally requires a large number of process steps. These steps include depositing an oxide layer on a substrate (not shown), depositing conductive layer
102
such as metal or polysilicon on the oxide layer, patterning conductive layer
102
to form the neck
108
, depositing an interlevel dielectric (not shown) over the patterned layer
102
, forming vias
104
and
106
in the interlevel dielectric, filling vias
104
and
106
with a metal from a metal layer formed over the interlevel dielectric, and patterning the metal layer (not shown) to form interconnects. In all, fabrication of fusible link
100
typically requires at least seven generalized, well-known steps. Additionally, the ability to scale down the size of fusible link
100
is constrained by, for example, a design rule requiring sufficient pitch, i.e. the width of conductive layer
102
plus spacing to adjacent conductors. Current processing operation limitations substantially limit pitch reductions. Furthermore, decreasing geometries increase the difficulty of reliably reproducing neck
108
to consistent parameters, which can lead to unpredictable operation. The integrity of neck
108
is necessary for normal operations, and an unintended disruption of current flow through fusible link
100
due to an unexpectedly small neck unexpectedly open-circuiting can result in failure of an entire circuit. Additionally, the programming current may unexpectedly fail to open circuit an unexpectedly large neck. Thus to assure programming, the programming current is generally increased to compensate for variations in neck
108
geometry. Moreover, the layout and chip area required by fusible link
100
adversely impact component packing densities.
Other fuse structures have been proposed such as the fuse structure in Crafts et al., U.S. Pat. No. 5,376,820. Crafts et al forms a junction between a normally sized aluminum via and a polysilicon layer. The polysilicon layer and via material conduct a limited current below the current necessary to internally melt the via. However, the polysilicon layer, having a high impedance relative to the via material, acts as a heating element and melts the aluminum via material at the junction to sever any connections between the via and the polysilicon layer. Additionally, Crafts et al. protects other vias from the current density needed to heat the polysilicon layer by providing parallel current paths into the polysilicon layer and a single path out through the junction.
Conventionally, filled vias and contact holes are sized to provide permanent conductive interconnections between conductors on different integrated circuit layers. Current supply circuitry is not designed to supply current sufficient to destroy a conventionally filled via or contact hole without unacceptably increasing the risk of damage to other conducting conductors and other adjacent structures.
SUMMARY OF THE INVENTION
The present invention, in one embodiment, provides a reliable fuse structure which, for example, may be fabricated with minimal process steps having sufficiently small dimensions and orientation to offer relatively high packing densities. Pitch constraints associated with conductive layers are generally inapplicable as the fusible interlevel interconnection may be narrower than associated overlying and underlying conductors. Additionally, embodiments of the present invention support repeatability and scalability of fabrication processes, predictability of programming currents, and relatively low programming currents. In one embodiment, an interlevel opening, such as a via or contact hole disposed within an isolation layer and between conducting layers, is filled with conductive material to form a programmable interlevel interconnection. Adjacent structures and associated current carrying structures including non-programmable filled vias and contact holes are sufficiently robust to conduct without being damaged by a programming current.
This may be achieved by, for example, reducing the current carrying capacity of the filled interlevel opening by using “undersized” dimensions. Although the programmable interlevel interconnection is undersized, normal operational current densities incurred, for example, during read operations, are intentionally limited to an acceptable level for long-term operational reliability. Also, because of undersized dimensions, programming currents sufficient to elevate current density in the programmable interlevel interconnection to destroy the fusible interlevel interconnection are ineffective to damage adjacent structures or associated current carrying structures. Current densities in “normally” sized conductors are kept at a reliable, long-term current density level.
The present invention, in another embodiment, includes a first conductor of an integrated circuit, a second conductor, and an isolation layer disposed between the first conductor and the second conductor, the isolation layer having an opening disposed through the isolation layer. A fusible interlevel interconnection, disposed in the opening, electrically connects the first and second conductors in a nonprogrammed state and electrically isolates the first and second conductors in a programmed state. The opening constrains and defines the cross-sectional area of the fusible interlevel interconnection so that a destructive programming current density may be developed within the fusible interlevel interconnection to program the fusible interlevel i
Hansen Anita M.
Lien Chuen-Der
Pilling David J.
Cao Phat X.
Integrated Device Technology Inc.
Skjerven Morrill & MacPherson LLP
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